IP Library Granted Patent US 12,713,526
Granted Patent B2
US 12,713,526 · App. 18/703,638 · Granted Aug 18, 2026

Wiring board and manufacturing method for the same

Inventor: Noriyuki Shimizu (Fukuchiyama, JP)
Assignee: KYOCERA CORPORATION
H05K1/0298H05K2201/09236H05K2201/095H05K2201/09727
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Quick Facts
Patent No.
US 12,713,526
App. No.
18/703,638
Granted
Aug 18, 2026
Kind
B2
Abstract

A wiring board according to the present disclosure includes an insulation layer, a groove located at an upper surface of the insulation layer, a recessed portion located at the upper surface of the insulation layer and having a width wider than the groove, an underlying metal layer located at an inner surface of the groove and an inner surface of the recessed portion, a first wiring conductor located on the underlying metal layer to fill the groove, and a second wiring conductor located on the underlying metal layer to fill the recessed portion and having a width wider than the first wiring conductor. The second wiring conductor includes a first portion and a second portion located adjacent to and integrally with the first portion. A plurality of voids are located at a boundary between the first portion and the second portion.

Claims (31)

1 . A wiring board comprising:

an insulation layer;

a groove located at an upper surface of the insulation layer;

a recessed portion located at the upper surface of the insulation layer and having a width wider than the groove;

an underlying metal layer located at an inner surface of the groove and an inner surface of the recessed portion;

a first wiring conductor located on the underlying metal layer to fill the groove; and

a second wiring conductor located on the underlying metal layer to fill the recessed portion and having a width wider than the first wiring conductor, wherein

the second wiring conductor comprises a first portion and a second portion located adjacent to and integrally with the first portion, and

a plurality of voids each having a maximum length in a range from 50 nm to 1 μm are located at a boundary between the first portion and the second portion.

2 . The wiring board according to claim 1 , wherein

the first portion is a first electrolytic plating metal, and the second portion is a second electrolytic plating metal.

3 . The wiring board according to claim 1 , wherein

at least a part of the first portion and of the second portion located with the boundary interposed therebetween contains a continuous crystal.

4 . The wiring board according claim 1 , wherein

the first wiring conductor has a width of 15 μm or less.

5 . The wiring board according to claim 1 , wherein

the second wiring conductor has a width of 150 μm or more.

6 . A manufacturing method for a wiring board, the manufacturing method comprising:

forming a groove and a recessed portion having a width wider than the groove, at an upper surface of an insulation layer;

forming an underlying metal layer at the upper surface of the insulation layer, an inner surface of the groove, and an inner surface of the recessed portion;

forming at least one plating resist having a width narrower than the width of the recessed portion, on the underlying metal layer in the recessed portion;

forming a first electrolytic plating layer on the underlying metal layer exposed from the plating resist;

removing the plating resist from on top of the underlying metal layer;

forming a second electrolytic plating layer on the first electrolytic plating layer and on the underlying metal layer; and

removing portions of the first electrolytic plating layer, the second electrolytic plating layer, and the underlying metal layer to form a first wiring conductor that fills the groove and is made of a first electrolytic plating metal derived from the first electrolytic plating layer or a second electrolytic plating metal derived from the second electrolytic plating layer, and a second wiring conductor that fills the recessed portion and is made of the first electrolytic plating metal derived from the first electrolytic plating layer and the second electrolytic plating metal derived from the second electrolytic plating layer, wherein the second wiring conductor comprises a first portion and a second portion located adjacent to and integrally with the first portion, and a plurality of voids each having a maximum length in a range from 50 nm to 1 μm are located at a boundary between the first portion and the second portion.

7 . The manufacturing method for the wiring board according to claim 6 , wherein

the plating resist has a width in a range from 50 μm to 100 μm.

8 . The manufacturing method for the wiring board according to claim 6 , wherein

the first wiring conductor has a width of 15 μm or less.

9 . The manufacturing method for the wiring board-according to claim 6 , wherein

the second wiring conductor has a width of 150 μm or more.