IP Library Granted Patent US 12713575
Granted Patent B2
US 12713575 · App. 18/585,516 · Granted Aug 18, 2026

Semiconductor device and method for fabricating the same

Inventors: Bo Min Park (Gyeonggi-do, KR); Wan Sup Shin (Gyeonggi-do, KR); Seung Mi Yeo (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H10B12/033H10B12/482H10B12/488H10W20/033
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12713575
App. No.
18/585,516
Granted
Aug 18, 2026
Kind
B2
Abstract

A method for fabricating a semiconductor device includes forming a stack body by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure; forming an opening in the stack body; forming a capping layer that exposes an edge of the third layer by horizontally recessing the second layer and the fourth layer from the opening; forming a liner structure on the capping layer and an edge of the third layer; forming a sacrificial liner material over the liner structure; recessing the sacrificial liner material and the liner structure to expose an edge of the third layer; forming a third layer pattern by recessing an exposed edge of the third layer; and forming a data storage element that is coupled to the third layer pattern.

Claims (56)

1 . A method for fabricating a semiconductor device, the method comprising:

forming a stack body by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure;

forming an opening in the stack body;

forming a capping layer that exposes an edge of the third layer by horizontally recessing the second layer and the fourth layer from the opening;

forming a liner structure on the capping layer and an edge of the third layer;

forming a sacrificial liner material over the liner structure;

recessing the sacrificial liner material and the liner structure to expose the edge of the third layer;

forming a third layer pattern by recessing the exposed edge of the third layer; and

forming a data storage element that is coupled to the third layer pattern.

2 . The method of claim 1 , further comprising:

before forming the third layer pattern,

forming an additional liner material that covers the recessed sacrificial liner material and the recessed liner structure.

3 . The method of claim 1 , wherein forming the liner structure includes:

forming a first liner material on the edge of the third layer by an oxidation process; and

conformally depositing a second liner material over the first liner material.

4 . The method of claim 1 , wherein the liner structure includes silicon oxide.

5 . The method of claim 1 , wherein the sacrificial liner material includes silicon nitride.

6 . The method of claim 1 , wherein forming the data storage element includes:

forming a first electrode that is coupled to the third layer pattern;

exposing an outer wall of the first electrode by selectively recessing the first layer, the fifth layer, and a portion of the liner structure;

forming a dielectric layer over the first electrode; and

forming a second electrode over the dielectric layer.

7 . The method of claim 1 , wherein the data storage element includes a capacitor.

8 . The method of claim 1 , wherein the third layer includes a semiconductor material or an oxide semiconductor material.

9 . The method of claim 1 , wherein the third layer includes a monocrystalline silicon layer.

10 . The method of claim 1 , wherein the first layer and the fifth layer include silicon oxide, and the second layer and the fourth layer include silicon nitride.

11 . A method for fabricating a semiconductor device, the method comprising:

forming a stack body by sequentially forming a first layer, a second layer, a third layer, a fourth layer, and a fifth layer over a lower structure;

forming a first opening in the stack body;

through the first opening, replacing a portion of the second layer and a portion of the fourth layer with horizontal conductive lines;

forming a vertical conductive line that is coupled to a first edge of the third layer while filling the first opening;

forming a second opening in the stack body;

forming a capping layer that exposes a second edge of the third layer by horizontally recessing the second layer and the fourth layer from the second opening;

forming a liner structure over the capping layer and the second edge of the third layer;

forming a sacrificial liner material over the liner structure;

recessing the sacrificial liner material and the liner structure to expose the second edge of the third layer;

forming a third layer pattern by recessing the exposed second edge of the third layer; and

forming a data storage element that is coupled to the third layer pattern.

12 . The method of claim 11 , further comprising:

before forming the third layer pattern,

forming an additional liner material that covers the recessed sacrificial liner material and the recessed liner structure.

13 . The method of claim 11 , wherein forming the liner structure includes:

forming a first liner material over the second edge of the third layer by an oxidation process; and

depositing a second liner material conformally over the first liner material.

14 . The method of claim 11 , wherein the liner structure includes silicon oxide.

15 . The method of claim 11 , wherein the sacrificial liner material includes silicon nitride.

16 . The method of claim 11 , wherein forming the data storage element includes:

forming a first electrode that is coupled to the third layer pattern;

exposing an outer wall of the first electrode by selectively recessing the first layer, the fifth layer, and a portion of the liner structure;

forming a dielectric layer over the first electrode; and

forming a second electrode over the dielectric layer.

17 . The method of claim 11 , wherein the data storage element includes a capacitor.

18 . The method of claim 11 , wherein the third layer includes a semiconductor material or an oxide semiconductor material.

19 . The method of claim 11 , wherein the third layer includes a monocrystalline silicon layer.

20 . The method of claim 11 , wherein the first layer and the fifth layer include silicon oxide, and

the second layer and the fourth layer include silicon nitride.