Semiconductor devices
A semiconductor device includes a gate structure on a substrate, an insulating interlayer on the substrate and covering a sidewall of the gate structure, a capping layer on the gate structure and the insulating interlayer, a wiring on the capping layer, an insulation pattern on a bottom and a sidewall of an opening extending through the wiring and at least an upper portion of the capping layer, and an etch stop layer on the insulation pattern and the wiring. The insulation pattern includes a lower portion on the bottom of the opening and a lateral portion contacting the sidewall of the opening. A thickness of the lower portion of the insulation pattern from the bottom of the opening in a vertical direction is greater than a thickness of the lateral portion of the insulation pattern from the sidewall of the opening in a horizontal direction.
1 . A semiconductor device comprising:
a first gate structure and a second gate structure on a substrate;
an insulating interlayer on the substrate, the insulating interlayer covering a sidewall of each of the first gate structure and the second gate structure;
a capping layer on the first gate structure, the second gate structure, and the insulating interlayer;
a wiring on the capping layer;
an insulation pattern on a bottom and a sidewall of an opening, the opening extending through the wiring and at least an upper portion of the capping layer;
a first etch stop layer on the insulation pattern and the wiring; and
between the first gate structure and the second gate structure in a horizontal direction parallel to an upper surface of the substrate, a second etch stop layer covering a bottom surface of the insulating interlayer and the sidewall of each of the first gate structure and the second gate structure,
wherein the insulation pattern includes:
a lower portion on the bottom of the opening; and
a lateral portion contacting the sidewall of the opening, and
an upper portion on the lateral portion and an upper surface of the wiring,
wherein a thickness of the lower portion of the insulation pattern from the bottom of the opening in a vertical direction perpendicular to the upper surface of the substrate is greater than a thickness of the lateral portion of the insulation pattern from the sidewall of the opening in the horizontal direction,
wherein a top surface of the lateral portion of the insulation pattern is at a higher level than a top surface of the lower portion of the insulation pattern, and
wherein the upper portion of the insulation pattern covers an upper surface of the lateral portion of the insulation pattern and the upper surface of the wiring in the vertical direction.
2 . The semiconductor device according to claim 1 , wherein the opening extends through the capping layer, and exposes the insulating interlayer.
3 . The semiconductor device according to claim 1 , wherein the insulating interlayer includes silicon oxide.
4 . The semiconductor device according to claim 1 , wherein the insulation pattern and the first etch stop layer include different materials from each other.
5 . The semiconductor device according to claim 1 , wherein each of the insulation pattern and the first etch stop layer includes silicon nitride, silicon carbonitride or silicon boron nitride.
6 . The semiconductor device according to claim 1 , wherein the insulation pattern and the first etch stop layer include the same material.
7 . The semiconductor device according to claim 1 , wherein a portion of the first etch stop layer in the opening has a concave upper surface.
8 . The semiconductor device according to claim 1 , wherein the thickness of the lower portion of the insulation pattern in the vertical direction is greater than a thickness of the first etch stop layer.
9 . A semiconductor device comprising:
a gate structure on a substrate;
an insulating interlayer on the substrate, the insulating interlayer covering a sidewall of the gate structure;
a capping layer on the gate structure and the insulating interlayer;
a wiring on the capping layer; and
an insulation pattern on an upper surface of the capping layer and on a bottom and a sidewall of an opening, the opening extending through the wiring and at least an upper portion of the capping layer,
wherein the insulation pattern includes:
a lower portion on the bottom of the opening;
a lateral portion contacting the sidewall of the opening; and
an upper portion on the lateral portion and an upper surface of the wiring,
wherein a thickness of the lower portion of the insulation pattern from the bottom of the opening in a vertical direction perpendicular to an upper surface of the substrate is greater than a thickness of the lateral portion of the insulation pattern from the sidewall of the opening in a horizontal direction parallel to the upper surface of the substrate, and
wherein an upper surface of the lower portion of the insulation pattern is exposed by the upper portion of the insulation pattern in the opening, and
wherein the upper portion of the insulation pattern covers an upper surface of the lateral portion of the insulation pattern and the upper surface of the wiring in the vertical direction.
10 . The semiconductor device according to claim 9 , wherein the thickness of the lower portion of the insulation pattern in the vertical direction is greater than a thickness of the upper portion of the insulation pattern.
11 . The semiconductor device according to claim 9 , wherein the opening extends through the capping layer, and exposes the insulating interlayer.
12 . The semiconductor device according to claim 9 , wherein the insulating interlayer includes silicon oxide.
13 . The semiconductor device according to claim 9 , wherein the insulation pattern includes silicon nitride, silicon carbonitride or silicon boron nitride.
14 . A semiconductor device comprising:
a substrate including a cell region and a peripheral circuit region;
a first active pattern on the cell region of the substrate;
a first gate structure buried at an upper portion of the first active pattern, the first gate structure extending in a first direction parallel to an upper surface of the substrate;
a bit line structure contacting a central upper surface of the first active pattern, the bit line structure extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction;
a contact plug structure on an end portion of the first active pattern;
a capacitor on the contact plug structure;
a second gate structure and a third gate structure on the peripheral circuit region of the substrate;
an insulating interlayer on the peripheral circuit region of the substrate and covering a sidewall of each of the second gate structure and the third gate structure;
a capping layer on the second gate structure, the third gate structure, and the insulating interlayer;
a wiring on the capping layer;
a first insulation pattern on a bottom and a sidewall of an opening, the opening extending through the wiring and at least an upper portion of the capping layer;
a first etch stop layer on the first insulation pattern and the wiring; and
between the second gate structure and the third gate structure in a horizontal direction parallel to an upper surface of the substrate, a second etch stop layer covering a bottom surface of the insulating interlayer and the sidewall of each of the second gate structure and the third gate structure,
wherein the first insulation pattern includes:
a lower portion on the bottom of the opening;
a lateral portion contacting the sidewall of the opening; and
an upper portion on the lateral portion and an upper surface of the wiring,
wherein a thickness of the lower portion of the first insulation pattern from the bottom of the opening in a vertical direction perpendicular to the upper surface of the substrate is greater than a thickness of the lateral portion of the first insulation pattern from the sidewall of the opening in the horizontal direction,
wherein a top surface of the lateral portion of the first insulation pattern is at a higher level than a top surface of the lower portion of the first insulation pattern, and
wherein the upper portion of the first insulation pattern covers an upper surface of the lateral portion of the first insulation pattern and the upper surface of the wiring in the vertical direction.
15 . The semiconductor device according to claim 14 , wherein:
the first active pattern is one of a plurality of first active patterns spaced apart from each other in each of the first direction and the second direction,
each of the plurality of first active patterns extends in a third direction having an acute angle with respect to the first direction and the second direction,
the bit line structure is one of a plurality of bit line structures spaced apart from each other in the first direction, and
the contact plug structure is disposed on an end portion of each of the plurality of first active patterns that extend in the third direction.
16 . The semiconductor device according to claim 15 , wherein the contact plug structure is one of a plurality of contact plug structures, the semiconductor device further comprising:
a second insulation pattern that fills a space between neighboring ones of the plurality of contact plug structures,
wherein the second insulation pattern includes a material the same as a material of the first insulation pattern.
17 . The semiconductor device according to claim 16 , further comprising:
a third etch stop layer on the second insulation pattern,
wherein the third etch stop layer includes a material the same as a material of the first etch stop layer.
18 . The semiconductor device according to claim 16 , wherein the second insulation pattern contacts an upper portion of each of the plurality of bit line structures.
19 . The semiconductor device according to claim 14 , wherein an upper surface of the capping layer is coplanar with an upper surface of the bit line structure.
20 . The semiconductor device according to claim 14 , wherein an upper surface of the contact plug structure is coplanar with the upper surface of the wiring.