Memory structure and manufacturing method thereof
A memory structure includes a substrate structure and a memory cell disposed on the substrate structure. The memory cell includes device layers stacked on the substrate structure, a word line, a first contact, and a second contact. The device layer includes a semiconductor layer, a first doped region, a second doped region, a channel region located between the first doped region and the second doped region, and a capacitor. The first and second doped regions and the channel region are disposed in the semiconductor layer. The capacitor includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first and second electrode layers. The word line is disposed on a sidewall of the channel layer. The first contact is electrically connected to the first doped regions. The second contact is electrically connected to the second electrode layers. A manufacturing method thereof is provided.
1 . A memory structure comprising:
a substrate structure; and
a memory cell disposed on the substrate structure, and comprising:
a plurality of device layers stacked on the substrate structure, wherein the device layer comprises:
a semiconductor layer;
a first doped region, a second doped region, and a channel region disposed in the semiconductor layer, wherein the channel region is located between the first doped region and the second doped region, and the first doped region, the channel region, and the second doped region are arranged in a direction parallel to a top surface of the substrate structure; and
a capacitor disposed on the semiconductor layer, and comprising a first electrode layer, a second electrode layer, and a dielectric layer, wherein the dielectric layer is located between the first electrode layer and the second electrode layer;
a word line disposed on a sidewall of the channel region;
a first contact disposed in the plurality of device layers, and electrically connected to the plurality of first doped regions; and
a second contact disposed in the plurality of device layers, and electrically connected to the plurality of second electrode layers.
2 . The memory structure according to claim 1 , wherein the first electrode layer and the first doped region are located on different sides of the channel region, and the first electrode layer and the second doped region are located on the same side of the channel region.
3 . The memory structure according to claim 1 , wherein the first electrode layer is electrically connected to the second doped region.
4 . The memory structure according to claim 1 , wherein a width of the second electrode layer is greater than a width of the first electrode layer.
5 . The memory structure according to claim 1 , wherein the word line is disposed across the plurality of device layers.
6 . The memory structure according to claim 1 , wherein the semiconductor layer has a first surface and a second surface opposite to each other, the capacitor is disposed on the first surface of the semiconductor layer, and the device layer further comprises:
a first bonding layer disposed on the second surface of the semiconductor layer; and
a second bonding layer disposed on the capacitor and the semiconductor layer.
7 . The memory structure according to claim 6 , wherein
an end of the first bonding layer exceeds an end of the semiconductor layer, and
the dielectric layer is further located between the second electrode layer and the first bonding layer.
8 . The memory structure according to claim 6 , wherein the first bonding layer of one of adjacent two of the device layers is bonded to the second bonding layer of the other one of the adjacent two of the device layers.
9 . The memory structure according to claim 6 , wherein the substrate structure comprises:
a substrate; and
a third bonding layer disposed on the substrate, wherein the first bonding layer in the device layer closest to the substrate structure is bonded to the third bonding layer.
10 . The memory structure according to claim 1 , wherein a material of the dielectric layer comprises a high dielectric constant material.
11 . The memory structure according to claim 1 , further comprising:
a gate dielectric layer located between the word line and the channel region.