Memory cell and memory device
A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.
1 . A memory cell, comprising:
a substrate;
an active layer spaced apart from a surface of the substrate and including a channel extending in a direction which is parallel to the surface of the substrate;
a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate;
a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and
a word line vertically spaced apart from the active layer and extending in a direction crossing the active layer,
wherein the channel of the active layer includes round sidewalls having protrusions vertically overlapping with the word line.
2 . The memory cell of claim 1 , wherein the channel includes:
a first round sidewall having a first protrusion; and
a second round sidewall having a second protrusion,
wherein the first round sidewall and the second round sidewall face each other in a direction that the word line extends.
3 . The memory cell of claim 2 , wherein the first round sidewall includes first round sub-sidewalls that are symmetrical to each other with the first protrusion therebetween, and
the second round sidewall includes second round sub-sidewalls that are symmetrical to each other with the second protrusion therebetween.
4 . The memory cell of claim 1 , wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall facing each other.
5 . The memory cell of claim 4 , wherein each of the first notch-shaped sidewall and the second notch-shaped sidewall includes a plurality of flat surfaces and a plurality of recessed surfaces.
6 . The memory cell of claim 5 , wherein the flat surfaces and the recessed surfaces alternate in the direction that the word line extends.
7 . The memory cell of claim 6 , wherein the flat surfaces are adjacent to the bit line.
8 . The memory cell of claim 6 , wherein the recessed surfaces include a hemispherical notch shape, a triangular notch shape, or a rectangular notch shape.
9 . The memory cell of claim 4 , further comprising:
a dielectric supporter supporting each of the first notch-shaped sidewall and the second notch-shaped sidewall of the word line.
10 . The memory cell of claim 1 , wherein the word line has a double word line structure in which two word lines vertically face each other with the active layer interposed therebetween.
11 . The memory cell of claim 1 , wherein the word line includes a notch-shaped word line and a notch-shaped shield word line that vertically face each other with the active layer interposed therebetween.
12 . The memory cell of claim 1 , wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other,
wherein each of the first notch-shaped sidewall and the second notch-shaped sidewall includes a plurality of flat surfaces and a plurality of recessed surfaces, and
wherein a distance between the flat surfaces and the bit line is shorter than a distance between the recessed surfaces and the bit line.