Semiconductor device and manufacturing method therefor
A semiconductor device includes a substrate including a first area and a second area planarly surrounding the first area, a lower electrode disposed on the first area of the substrate and extending in a vertical direction, a supporter surrounding a sidewall of the lower electrode and supporting the lower electrode, a first upper electrode covering the lower electrode, on the lower electrode, the first upper electrode including a first portion disposed within the first area and a second portion disposed within the second area, a dielectric layer arranged between the lower electrode and the first upper electrode, and a second upper electrode disposed on the first portion of the first upper electrode, wherein the second upper electrode is not disposed on the second portion of the first upper electrode.
1 . A semiconductor device comprising:
a substrate comprising a first area and a second area planarly surrounding the first area;
a lower electrode disposed on the first area of the substrate and extending in a vertical direction;
a supporter surrounding a sidewall of the lower electrode and supporting the lower electrode;
a first upper electrode covering the lower electrode, on the lower electrode, the first upper electrode comprising a first portion disposed within the first area and a second portion disposed within the second area;
a dielectric layer arranged between the lower electrode and the first upper electrode; and
a second upper electrode disposed on the first portion of the first upper electrode,
wherein the second upper electrode is not disposed on, and does not vertically overlap, the second portion of the first upper electrode.
2 . The semiconductor device of claim 1 , wherein the first upper electrode comprises one or more selected from among silicon-germanium (SiGe) and silicon (Si), and
the second upper electrode comprises one or more selected from among tungsten (W), titanium nitride (TiN), and a combination thereof.
3 . The semiconductor device of claim 1 , wherein the second portion of the first upper electrode comprises a different material from a material of the second upper electrode.
4 . The semiconductor device of claim 1 , further comprising a protective layer on the second upper electrode, the protective layer comprising an insulating material.
5 . The semiconductor device of claim 4 , wherein the protective layer is not disposed on the second portion of the first upper electrode.
6 . The semiconductor device of claim 1 , wherein the second portion of the first upper electrode has an L-shaped cross-section.
7 . The semiconductor device of claim 1 , wherein the second portion of the first upper electrode comprises one or more protrusions protruding in a horizontal direction crossing the vertical direction, and
wherein at least part of one protrusion of the one or more protrusions overlaps the supporter in the horizontal direction.
8 . A semiconductor device comprising:
a substrate comprising a cell area and a connection area, the cell area comprising a first area and a second area, the second area being arranged horizontally between the first area and the connection area;
a plurality of conductive patterns disposed on the cell area of the substrate;
a plurality of lower electrodes respectively connected to the plurality of conductive patterns and each extending in a vertical direction;
a plurality of supporters surrounding each of a plurality of sidewalls of the plurality of lower electrodes and supporting the plurality of lower electrodes;
a dielectric layer disposed on the plurality of lower electrodes and the plurality of supporters and not disposed within the connection area;
a first upper electrode disposed on the dielectric layer, the first upper electrode comprising a first portion disposed within the first area and a second portion disposed within the second area; and
a second upper electrode disposed within the first area and not disposed within the second area and the connection area.
9 . The semiconductor device of claim 8 , wherein the first upper electrode comprises one or more selected from among silicon-germanium (SiGe) and silicon (Si), and
the second upper electrode comprises one or more selected from among tungsten (W), titanium nitride (TiN), and a combination thereof.
10 . The semiconductor device of claim 8 , wherein the second portion of the first upper electrode comprises one or more protrusions protruding in a horizontal direction crossing the vertical direction, and
at least part of one protrusion of the one or more protrusions overlaps the plurality of supporters in the horizontal direction.
11 . The semiconductor device of claim 8 , wherein the second portion of the first upper electrode comprises a tail portion protruding toward the connection area.
12 . The semiconductor device of claim 8 , wherein an upper surface of the second portion of the first upper electrode comprises a portion that is at a vertical level that is different from a vertical level of an upper surface of the first portion of the first upper electrode.
13 . The semiconductor device of claim 8 , further comprising a protective layer disposed on the second upper electrode, the protective layer comprising an insulating layer,
wherein the protective layer is not disposed on the second portion of the first upper electrode.
14 . The semiconductor device of claim 8 , wherein the plurality of conductive patterns are disposed on the first area and are not disposed on the second area.
15 . A semiconductor device comprising:
a substrate comprising a cell area, a connection area, and a peripheral circuit area, the cell area comprising a first area and a second area, the second area being arranged between the first area and the connection area;
a cell transistor disposed within the cell area of the substrate;
a peripheral circuit disposed within the peripheral circuit area of the substrate;
a capacitor disposed within the cell area of the substrate and electrically connected to the cell transistor; and
a peripheral circuit contact disposed within the peripheral circuit area of the substrate and electrically connected to the peripheral circuit,
wherein the capacitor comprises:
a lower electrode disposed on the first area of the substrate and extending in a vertical direction;
a plurality of supporters surrounding a sidewall of the lower electrode and supporting the lower electrode;
a first upper electrode covering the lower electrode, on the lower electrode, the first upper electrode comprising a first portion disposed within the first area and a second portion disposed within the second area;
a dielectric layer arranged between the lower electrode and the first upper electrode; and
a second upper electrode disposed on the first portion of the first upper electrode,
wherein the second upper electrode is not disposed on, and does not vertically overlap, the second portion of the first upper electrode.
16 . The semiconductor device of claim 15 , wherein the first upper electrode comprises one or more selected from among silicon-germanium (SiGe) and silicon (Si), and
the second upper electrode comprises one or more selected from among tungsten (W), titanium nitride (TiN), and a combination thereof.
17 . The semiconductor device of claim 15 , wherein the second portion of the first upper electrode comprises a different material from a material of the second upper electrode.
18 . The semiconductor device of claim 15 , wherein the second portion of the first upper electrode does not comprise tungsten (W), or titanium nitride (TiN).
19 . The semiconductor device of claim 15 , further comprising a protective layer disposed on the second upper electrode, the protective layer comprising an insulating material,
wherein the protective layer is not disposed on the second portion of the first upper electrode.
20 . The semiconductor device of claim 15 , wherein the second portion of the first upper electrode comprises one or more selected from among one or more protrusions protruding toward the connection area in a horizontal direction crossing the vertical direction and a tail portion protruding toward the connection area in the horizontal direction,
wherein at least part of one protrusion of the one or more protrusions overlaps the plurality of supporters in the horizontal direction, and
wherein a lower surface of the tail portion is at the same vertical level at which a lower surface of the second portion of the first upper electrode is located.