Semiconductor device and method of forming the same

1 . A semiconductor device, comprising:

a substrate comprising a cell region and a periphery region;

a plurality of storage node pads disposed on the substrate and located in the cell region;

a capacitor structure disposed on the plurality of storage node pads and comprising a plurality of bottom electrodes, a capacitor dielectric layer and a top electrode layer stacked in sequence, the plurality of bottom electrodes in contact with the plurality of storage node pads, respectively;

a supporting structure disposed on the plurality of storage node pads and interleaved among the plurality of bottom electrodes while being in physical contact with the plurality of bottom electrodes, the supporting structure comprising a first supporting layer and a second supporting layer sequentially from bottom to top, wherein the second supporting layer comprises a first portion having a first thickness, and a stepped portion partially having the first thickness and partially a second thickness, the stepped portion where has the first thickness is leveled with the first portion, and where has the second thickness is higher than the first portion, and the second thickness is greater than the first thickness, and wherein the first portion is disposed in the cell region and the stepped portion is disposed between the cell region and the periphery region;

an interlayer dielectric layer, disposed on the capacitor structure, overlaying the top electrode layer; and

a plug, disposed in the interlayer dielectric layer and electrically connected to the capacitor structure.

2 . The semiconductor device according to claim 1 , wherein a top surface of the second supporting layer with the first thickness is coplanar with a top surface of the plurality of bottom electrodes.

3 . The semiconductor device according to claim 2 , wherein a bottom surface of the stepped portion is coplanar with a bottom surface of the first portion.

4 . The semiconductor device according to claim 2 , wherein sidewalls of the stepped portion is in contact with both the capacitive dielectric layer and one of the plurality of bottom electrodes.

5 . The semiconductor device according to claim 4 , wherein the sidewalls of the stepped portion has a side close to the cell region and an opposite side away from the cell region, and the side of the sidewalls close to the cell region is in physical contact with the one of the plurality of bottom electrodes, while the opposite side of the sidewalls away from the cell region is in physical contact with the capacitive dielectric layer.

6 . The semiconductor device according to claim 1 , wherein a level of the second supporting layer with the second thickness relative to the substrate is greater than a level of the second supporting layer with the first thickness relative to the substrate.

7 . The semiconductor device according to claim 1 , wherein a topmost surface of the stepped portion is coplanar with a top surface of one of the plurality of bottom electrodes, and a top surface of the first portion is lower than the top surface of the one of the plurality of bottom electrodes.

8 . The semiconductor device according to claim 7 , wherein a bottom surface of the stepped portion is coplanar with a bottom surface of the first portion.

9 . The semiconductor device according to claim 1 , wherein the capacitive dielectric layer are in physical contact with both sides of sidewalls of the second supporting layer with the second thickness.

10 . The semiconductor device according to claim 1 , wherein each of the plurality of bottom electrodes comprises a U-shaped electrode structure or a columnar electrode structure.

11 . A semiconductor device, comprising:

a substrate comprising a cell region and a periphery region;

a plurality of storage node pads disposed on the substrate and located in the cell region;

a capacitor structure disposed on the plurality of storage node pads and comprising a plurality of bottom electrodes, in contact with the plurality of storage node pads, respectively; and

a supporting structure disposed on the plurality of storage node pads and interleaved among the plurality of bottom electrodes while being in physical contact with the plurality of bottom electrodes, the supporting structure comprising a first supporting layer and a second supporting layer sequentially from bottom to top, wherein the second supporting layer comprises a first thickness and a second thickness and the second thickness is greater than the first thickness, and wherein the second supporting layer having the first thickness is disposed in the cell region and the second supporting layer having the second thickness is disposed between the cell region and the periphery region;

wherein a top surface of the second supporting layer having the first thickness, and a top surface of the second supporting layer having the second thickness are respectively lower than a top surface of a corresponding one of the plurality of bottom electrodes.

12 . The semiconductor device according to claim 11 , wherein a bottom surface of the second supporting layer having the second thickness is coplanar with a bottom surface of the second supporting layer having the first thickness.

13 . The semiconductor device according to claim 11 , wherein the capacitor structure further comprises a capacitive dielectric layer and a top electrode layer stacked in sequence, and sidewalls of the second supporting layer having the second thickness is in contact with both the capacitive dielectric layer and one of the plurality of bottom electrodes.

14 . The semiconductor device according to claim 13 , wherein the sidewalls of the second supporting layer having the second thickness has a side close to the cell region and an opposite side away from the cell region, and the side of the sidewalls close to the cell region is in physical contact with the one of the plurality of bottom electrodes, while the opposite side of the sidewalls away from the cell region is in physical contact with the capacitive dielectric layer.

15 . The semiconductor device according to claim 11 , wherein a level of the second supporting layer having the second thickness relative to the substrate is greater than a level of the second supporting layer having the first thickness relative to the substrate.

16 . The semiconductor device according to claim 11 , wherein each of the plurality of bottom electrodes comprises a U-shaped electrode structure or a columnar electrode structure.

17 . A semiconductor device, comprising:

a substrate comprising a cell region and a periphery region;

a plurality of storage node pads disposed on the substrate and located in the cell region;

a capacitor structure disposed on the plurality of storage node pads and comprising a plurality of bottom electrodes, in contact with the plurality of storage node pads, respectively; and

a supporting structure disposed on the plurality of storage node pads and interleaved among the plurality of bottom electrodes while being in physical contact with the plurality of bottom electrodes, the supporting structure comprising a first supporting layer and a second supporting layer sequentially from bottom to top, wherein the second supporting layer comprises a first thickness and a second thickness and the second thickness is greater than the first thickness, and wherein the second supporting layer having the first thickness is disposed in the cell region and the second supporting layer having the second thickness is disposed between the cell region and the periphery region;

wherein a top surface of one of the plurality of bottom electrodes in direct contact with the second supporting layer comprising the second thickness is higher than a top surface of one of the plurality of bottom electrodes in direct contact with the second supporting layer comprising the first thickness.

18 . The semiconductor device according to claim 17 , wherein a bottom surface of the second supporting layer having the second thickness is coplanar with a bottom surface of the second supporting layer having the first thickness.

19 . The semiconductor device according to claim 17 , wherein the capacitor structure further comprises a capacitive dielectric layer and a top electrode layer stacked in sequence, and sidewalls of the second supporting layer having the second thickness is in contact with both the capacitive dielectric layer and one of the plurality of bottom electrodes.

20 . The semiconductor device according to claim 19 , wherein the sidewalls of the second supporting layer having the second thickness has a side close to the cell region and an opposite side away from the cell region, and the side of the sidewalls close to the cell region is in physical contact with the one of the plurality of bottom electrodes, while the opposite side of the sidewalls away from the cell region is in physical contact with the capacitive dielectric layer.