Semiconductor element, electronic system including the semiconductor element, and method of fabricating the semiconductor element
A semiconductor element may include a substrate including source and drain regions formed in the substrate apart from each other by a trench, a gate insulating layer covering a bottom surface and a sidewall of the trench, a gate electrode including lower and upper buried portions. The lower buried portion may be in the trench with the gate insulating layer therearound and fill a lower region of the trench. The upper buried portion may be on the lower buried portion with the gate insulating layer therearound and fill an upper region of the trench. The upper buried portion may include a two-dimensional material layer in the trench on an upper surface of the first conductive layer and an upper region of the sidewall of the gate insulating layer, and a second conductive layer in the upper region of the trench and surrounded by the two-dimensional material layer.
1 . A semiconductor element comprising:
a substrate comprising a trench, a source region, and a drain region,
the source region and the drain region separated apart from each other by the trench;
a gate insulating layer covering a bottom surface and a sidewall of the trench;
a gate electrode comprising a lower buried portion and an upper buried portion with the gate insulating layer therearound,
the lower buried portion filling a lower region of the trench, and
the upper buried portion being on the lower buried portion and filling an upper region of the trench; and
a capping layer on the gate electrode,
wherein the lower buried portion comprises a barrier layer and a first conductive layer,
the barrier layer is in the trench,
the barrier layer covers a bottom surface of the gate insulating layer and a lower region of a sidewall of the gate insulating layer,
the barrier layer surrounds the first conductive layer,
the first conductive layer fills the lower region of the trench, and
the lower buried portion does not overlap the source region and the drain region, and
wherein the upper buried portion comprises a two-dimensional material layer and a second conductive layer,
the two-dimensional material layer is in the trench,
the two-dimensional material layer covers an upper surface of the first conductive layer and an upper region of the sidewall of the gate insulating layer,
the two-dimensional material layer surrounds the second conductive layer,
the second conductive layer fills the upper region of the trench, and
the upper buried portion overlaps the source region and the drain region, wherein a first dielectric constant of a lower region of the gate insulating layer is greater than a second dielectric constant of an upper region of the gate insulating layer.
2 . The semiconductor element of claim 1 ,
wherein a work function of the second conductive layer is less than a work function of the first conductive layer.
3 . The semiconductor element of claim 1 ,
wherein a work function of the second conductive layer is about 2 eV to about 5 eV.
4 . The semiconductor element of claim 1 ,
wherein the second conductive layer comprises at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).
5 . The semiconductor element of claim 1 ,
wherein the two-dimensional material layer comprises at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, and a transition metal dichalcogenide.
6 . A semiconductor element comprising:
a substrate comprising a trench, a source region, and a drain region,
the source region and the drain region separated apart from each other by the trench;
a gate insulating layer covering a bottom surface and a sidewall of the trench;
a gate electrode comprising a lower buried portion and an upper buried portion with the gate insulating layer therearound,
the lower buried portion filling a lower region of the trench, and
the upper buried portion being on the lower buried portion and filling an upper region of the trench; and
a capping layer on the gate electrode,
wherein the lower buried portion comprises a barrier layer and a first conductive layer,
the barrier layer is in the trench,
the barrier layer covers a bottom surface of the gate insulating layer and a lower region of a sidewall of the gate insulating layer,
the barrier layer surrounds the first conductive layer,
the first conductive layer fills the lower region of the trench, and
the lower buried portion does not overlap the source region and the drain region, and
wherein the upper buried portion comprises a two-dimensional material layer and a second conductive layer,
the two-dimensional material layer is in the trench,
the two-dimensional material layer covers an upper surface of the first conductive layer and an upper region of the sidewall of the gate insulating layer,
the two-dimensional material layer surrounds the second conductive layer,
the second conductive layer fills the upper region of the trench,
the upper buried portion overlaps the source region and the drain region, wherein the two-dimensional material layer directly contacts the gate insulating layer, and
wherein a first dielectric constant of a lower region of the gate insulating layer is greater than a second dielectric constant of an upper region of the gate insulating layer.
7 . The semiconductor element of claim 1 ,
the lower region of the gate insulating layer surrounds the barrier layer, and
the upper region of the gate insulating layer surrounds the two-dimensional material layer.
8 . The semiconductor element of claim 1 ,
wherein a material in the first conductive layer is different from a material in the second conductive layer.
9 . An electronic system comprising:
a controller;
a memory configured to store instructions executed by the controller, the memory comprising the semiconductor element of claim 1 ; and
an input/output device coupled to the controller.
10 . A semiconductor element comprising:
a substrate comprising a trench, a source region, and a drain region,
the source region and the drain region separated apart from each other by the trench;
a gate insulating layer covering a bottom surface and a sidewall of the trench;
a gate electrode comprising a barrier layer, a two-dimensional material layer, and a conductive layer; and
a capping layer on the gate electrode,
wherein the gate insulating layer surrounds the barrier layer,
the barrier layer is in the trench,
the barrier layer covers a bottom surface of the gate insulating layer and a lower region of a sidewall of the gate insulating layer,
the two-dimensional material layer covers an upper region of the sidewall of the gate insulating layer in the trench, and
the conductive layer is in the trench and includes a first conductive layer surrounded by the barrier layer and a second conductive layer surrounded by the two-dimensional material layer,
wherein the barrier layer does not overlap the source region and the drain region, and
the two-dimensional material layer overlaps the source region and the drain region,
a material in the first conductive layer is different from a material in the second conductive layer, and
wherein a first dielectric constant of a lower region of the gate insulating layer is greater than a second dielectric constant of an upper region of the gate insulating layer.
11 . The semiconductor element of claim 10 ,
wherein the second conductive layer comprises at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).
12 . The semiconductor element of claim 10 ,
wherein the two-dimensional material layer comprises at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, and a transition metal dichalcogenide.
13 . The semiconductor element of claim 6 ,
wherein the two-dimensional material layer comprises at least one of graphene, black phosphorus, amorphous Boron Nitride, two-dimensional hexagonal boron nitride (h-BN), phosphorene, and a transition metal dichalcogenide.
14 . The semiconductor element of claim 6 ,
wherein a first thickness of a lower region of the gate insulating layer is less than a second thickness of an upper region of the gate insulating layer,
the lower region of the gate insulating layer surrounds the barrier layer, and
the upper region of the gate insulating layer surrounds the two-dimensional material layer.
15 . The semiconductor element of claim 1 , wherein the two-dimensional material layer directly contacts the gate insulating layer.
16 . The semiconductor element of claim 10 , wherein the two-dimensional material layer directly contacts the gate insulating layer.
17 . The semiconductor element of claim 6 ,
wherein a work function of the second conductive layer is less than a work function of the first conductive layer,
wherein the second conductive layer comprises at least one of aluminum (Al), titanium (Ti), chromium (Cr), gold (Au), nickel (Ni), and platinum (Pt).
18 . The semiconductor element of claim 10 , wherein
the lower region of the gate insulating layer surrounds the barrier layer, and
the upper region of the gate insulating layer surrounds the two-dimensional material layer.
19 . The semiconductor element of claim 6 ,
wherein the lower region of the gate insulating layer surrounds the barrier layer, and
the upper region of the gate insulating layer surrounds the two-dimensional material layer.