Semiconductor device having word lines embedded in gate trenches formed in STI regions and active regions of a semiconductor substrate

1 . An apparatus comprising:

a semiconductor substrate having first and second gate trenches arranged in parallel and extending in a first direction; and

first and second gate electrodes embedded in the first and second gate trenches, respectively, via a gate insulating film,

wherein each of the first and second gate electrodes includes a first conductive film located at a bottom of the respective first and second gate trenches and a second conductive film stacked on the first conductive film,

wherein the second conductive film included in a first portion of the second gate electrode is thinner than the second conductive film included in a first portion of the first gate electrode which is arranged adjacent to the first portion of the second gate electrode in a second direction crossing the first direction,

wherein the second conductive film is lower in work function than the first conductive film, and

wherein a depth position of an interface between the first conductive film and the second conductive film is the same in the first gate electrode and in the second gate electrode.

2 . The apparatus of claim 1 ,

wherein the first portion of the first gate electrode is sandwiched in an active region of the semiconductor substrate in the second direction, and

wherein the first portion of the second gate electrode is sandwiched in an STI region in the second direction.

3 . The apparatus of claim 1 , wherein a first portion of the second gate trench embedding the first portion of the second gate electrode is deeper than a first portion of the first gate trench embedding the first portion of the first gate electrode.

4 . The apparatus of claim 3 , wherein the first conductive film included in the first portion of the second gate electrode is thicker than the first conductive film included in the first portion of the first gate electrode.

5 . The apparatus of claim 4 , wherein the first conductive film comprises metal material.

6 . The apparatus of claim 5 , wherein the first conductive film comprises titanium nitride.

7 . The apparatus of claim 5 , wherein the second conductive film comprises polycrystalline silicon.

8 . The apparatus of claim 3 ,

wherein the semiconductor substrate further has a third gate trench, a first source/drain region located between the first portion of the first gate trench and the first portion of the second gate trench, and a second source/drain region located between the first portion of the first gate trench and a first portion of the third gate trench which is arranged adjacent to the first portion of the first gate electrode in the second direction,

wherein the apparatus further comprises:

a third gate electrode embedded in the third gate trench via the gate insulating film;

a first cell capacitor coupled to the first source/drain region; and

a bit line coupled to the second source/drain region.

9 . The apparatus of claim 8 ,

wherein the third gate electrode includes the first conductive film located at a bottom of the third gate trench and the second conductive film stacked on the first conductive film, and

wherein the second conductive film included in the first portion of the second gate electrode is thinner than the second conductive film included in the first portion of the third gate electrode.

10 . The apparatus of claim 9 ,

wherein the semiconductor substrate further has a fourth gate trench and a third source/drain region located between the first portion of the third gate trench and a first portion of the fourth gate trench which is arranged adjacently to the first portion of the third gate electrode in the second direction,

wherein the apparatus further comprises:

a fourth gate electrode embedded in the fourth gate trench via the gate insulating film; and

a second cell capacitor coupled to the third source/drain region,

wherein the fourth gate electrode includes the first conductive film located at a bottom of the fourth gate trench and the second conductive film stacked on the first conductive film, and

wherein the second conductive film included in the first portion of the fourth gate electrode is thinner than the second conductive film included in the first portion of the third gate electrode.

11 . A semiconductor substrate having first and second gate trenches arranged in parallel and extending in a first direction; and

first and second gate electrodes embedded in the first and second gate trenches, respectively, via a gate insulating film,

wherein each of the first and second gate electrodes includes a first conductive film located at a bottom of the respective first and second gate trenches and a second conductive film stacked on the first conductive film,

wherein the second conductive film included in a first portion of the second gate electrode is thinner than the second conductive film included in a first portion of the first gate electrode which is arranged adjacent to the first portion of the second gate electrode in a second direction crossing the first direction,

wherein the second conductive film is lower in work function than the first conductive film,

wherein each of the first and second gate electrodes includes a cap insulating film stacked on the second conductive film, and

wherein a depth position of an interface between the second conductive film and the cap insulating film is deeper in the second gate electrode than in the first gate electrode.