Memory device and forming method thereof
The present disclosure provides a memory device and the forming method thereof. The memory device includes a bit line on a substrate, a multilayer spacer covering the bit line, a low-k dielectric layer and an air gap interposed in the multilayer spacer, and a cell contact adjacent to the multilayer spacer. The multilayer spacer, the low-k dielectric layer, and the air gap are disposed between the bit line and the cell contact. The top surface of the low-k dielectric layer is lower than a top surface of the bit line. The air gap is above the low-k dielectric layer, and an orthogonal projection of the air gap onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate.
1 . A memory device, comprising:
a bit line on a substrate;
a multilayer spacer covering the bit line, comprising:
a first spacer layer covering a sidewall and a top surface of the bit line;
a second spacer layer covering a low-k dielectric layer and the first spacer layer; and
a third spacer layer covering an air gap and the second spacer layer;
the low-k dielectric layer interposed in the multilayer spacer, wherein a top surface of the low-k dielectric layer is lower than the top surface of the bit line;
the air gap interposed in the multilayer spacer, wherein the air gap is above the low-k dielectric layer, and an orthogonal projection of the air gap onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate; and
a cell contact adjacent to the multilayer spacer, wherein the multilayer spacer, the low-k dielectric layer, and the air gap are disposed between the bit line and the cell contact.
2 . The memory device of claim 1 , wherein the top surface of the low-k dielectric layer is between the top surface of the bit line and a top surface of a work function layer in the bit line.
3 . The memory device of claim 1 , wherein a ratio of a height of the low-k dielectric layer to a height of the bit line is equal to or higher than 0.5.
4 . The memory device of claim 1 , wherein a dielectric constant of the low-k dielectric layer is in a range of 2.7 to 3.1.
5 . The memory device of claim 1 , wherein the low-k dielectric layer and the air gap are separated by the second spacer layer.
6 . The memory device of claim 1 , wherein a sidewall of the first spacer layer is parallel to a sidewall of the third spacer layer, and wherein the low-k dielectric layer, the second spacer layer, and the air gap are sandwiched between the sidewall of the first spacer layer and the sidewall of the third spacer layer.
7 . The memory device of claim 1 , wherein a thickness of the second spacer layer is smaller than a width of the low-k dielectric layer.
8 . The memory device of claim 1 , wherein a width of the air gap is equal to a width of the low-k dielectric layer.
9 . The memory device of claim 1 , wherein a top surface of the air gap is higher than the top surface of the bit line.
10 . The memory device of claim 1 , wherein the first spacer layer, the second spacer layer, and the third spacer layer comprises a same material.
11 . The memory device of claim 1 , wherein the second spacer layer directly contacts a top surface of the first spacer layer, and the third spacer layer directly contacts a top surface of the second spacer layer.
12 . The memory device of claim 1 , further comprising:
a landing pad above the bit line and the multilayer spacer, wherein the landing pad is electrically connected to the bit line through the multilayer spacer.