Semiconductor memory devices
A semiconductor device includes a substrate that includes an active pattern, a bit line structure that crosses the active pattern, a storage node contact electrically connected to the active pattern next to the bit line structure, a spacer structure between a side surface of the bit line structure and the storage node contact, an upper surface of the spacer structure is at a vertical level lower than an upper surface of the bit line structure, an insulating pattern on the spacer structure, and a landing pad structure electrically connected to the storage node contact and on the spacer structure and the bit line structure. The landing pad structure include a first side surface in contact with the spacer structure, a second side surface in contact with the bit line structure, and a third side surface in contact with the insulating pattern.
1 . A semiconductor memory device comprising:
a substrate that includes an active pattern;
a bit line structure that crosses the active pattern;
a storage node contact electrically connected to the active pattern next to the bit line structure;
a spacer structure between a side surface of the bit line structure and the storage node contact, wherein an upper surface of the spacer structure is at a vertical level lower than an upper surface of the bit line structure with a lower surface of the substrate providing a base reference plane;
an insulating pattern on the spacer structure; and
a landing pad structure electrically connected to the storage node contact and on the spacer structure and the bit line structure,
wherein the landing pad structure comprises:
a first side surface in contact with the spacer structure;
a second side surface in contact with the bit line structure; and
a third side surface in contact with the insulating pattern.
2 . The semiconductor device of claim 1 , wherein the landing pad structure has a stepped shape in a cross-sectional view.
3 . The semiconductor device of claim 1 , wherein the spacer structure includes a first spacer and a second spacer on an upper surface of the first spacer,
wherein the first spacer is a multilayer spacer, and
wherein the second spacer is a single-layer spacer.
4 . The semiconductor device of claim 3 , wherein the second spacer has a closed shape in a plan view, and
wherein the second spacer has a first height between the first spacer and the insulating pattern and a second height different from the first height between the first spacer and the landing pad structure.
5 . The semiconductor device of claim 1 , wherein the spacer structure comprises:
a first sub-spacer in contact with the bit line structure;
a second sub-spacer on a side surface of the first sub-spacer; and
a third sub-spacer in contact with the storage node contact,
wherein the second sub-spacer is between the first sub-spacer and the third sub-spacer.
6 . The semiconductor device of claim 1 , wherein the landing pad structure comprises:
a barrier pattern adjacent to the storage node contact; and
a landing pad adjacent to the insulating pattern,
wherein the landing pad includes a protruding portion between the barrier pattern and the bit line structure, and
wherein the protruding portion is vertically aligned with the spacer structure.
7 . The semiconductor device of claim 6 , wherein the barrier pattern includes a conductive material different from that of the landing pad.
8 . The semiconductor device of claim 1 , wherein a lower portion of the insulating pattern adjacent to the spacer structure is vertically aligned with the spacer structure.
9 . A semiconductor device comprising:
a substrate that includes an active pattern, the active pattern including a first source/drain region and a second source/drain region spaced apart from each other;
a bit line structure that is electrically connected to the first source/drain region and crosses the active pattern;
a storage node contact electrically connected to the second source/drain region;
a spacer structure on a side of the bit line structure, wherein an upper surface of the spacer structure is at a lower vertical level than an upper surface of the bit line structure with a lower surface of the substrate providing a base reference plane;
a landing pad structure electrically connected to the storage node contact; and
an insulating pattern on the spacer structure and adjacent to the landing pad structure,
wherein the spacer structure comprises:
a first spacer between the bit line structure and the storage node contact; and
a second spacer on an upper surface of the first spacer, and between the bit line structure and the landing pad structure,
wherein the first spacer is a multilayer spacer, and
wherein the second spacer is a single-layer spacer.
10 . The semiconductor device of claim 9 , wherein the landing pad structure has a stepped shape in a cross-sectional view.
11 . The semiconductor device of claim 9 , wherein the landing pad structure comprises:
a first side surface in contact with the spacer structure;
a second side surface in contact with the bit line structure; and
a third side surface in contact with the insulating pattern.
12 . The semiconductor device of claim 9 , wherein the first spacer comprises:
a first sub-spacer adjacent to the bit line structure;
a second sub-spacer on a side surface of the first sub-spacer; and
a third sub-spacer adjacent to the storage node contact,
wherein the second sub-spacer is between the first sub-spacer and the third sub-spacer.
13 . The semiconductor device of claim 9 , wherein the landing pad structure comprises:
a barrier pattern adjacent to the storage node contact; and
a landing pad adjacent to the insulating pattern, and
wherein the landing pad has a ‘T’-shaped cross section.
14 . The semiconductor device of claim 13 , wherein the barrier pattern includes a conductive material different from that of the landing pad.
15 . The semiconductor device of claim 13 , wherein a width of a lower surface of the landing pad is equal to a width of an upper surface of the spacer structure.
16 . The semiconductor device of claim 9 , wherein a width of a lower surface of the insulating pattern is equal to a width of an upper surface of the spacer structure.
17 . The semiconductor device of claim 9 , wherein the first spacer includes an oxide and a nitride, and
wherein the second spacer includes an oxide.
18 . A semiconductor memory device comprising:
a substrate that includes an active pattern, the active pattern including a first source/drain region and a pair of second source/drain regions spaced apart from each other with the first source/drain region therebetween;
a device isolation layer on the substrate and in a trench that defines the active pattern;
a word line extending in a first direction that crosses the active pattern, wherein the word line is between the first and second source/drain regions;
a gate dielectric layer between the word line and the active pattern;
a word line capping pattern on the word line;
an interlayer insulating pattern on the word line capping pattern;
a bit line structure electrically connected to the first source/drain region and extending in a second direction that intersects the first direction, wherein the bit line structure crosses the active pattern and is on the interlayer insulating pattern;
a spacer structure on a side surface of the bit line structure, wherein an upper surface of the spacer structure is at a lower vertical level than an upper surface of the bit line structure with a lower surface of the substrate providing a base reference plane;
a storage node contact electrically connected to at least one of the second source/drain regions, wherein the storage node contact is spaced apart from the bit line structure with the spacer structure therebetween;
a landing pad structure electrically connected to the storage node contact;
an insulating pattern on the spacer structure; and
a data storage pattern on the landing pad structure,
wherein the landing pad structure has a stepped shape in a cross-sectional view, and
wherein the spacer structure includes a multilayer spacer on the interlayer insulating pattern and a single-layer spacer on the multilayer spacer.
19 . The semiconductor device of claim 18 , wherein the landing pad structure comprises:
a first side surface in contact with the spacer structure;
a second side surface in contact with the bit line structure; and
a third side surface in contact with the insulating pattern.
20 . The semiconductor device of claim 18 , wherein the landing pad structure comprises:
a barrier pattern adjacent to the storage node contact; and
a landing pad adjacent to the insulating pattern, and
wherein the landing pad has a ‘T’-shaped cross section.