Semiconductor device and method of fabricating the same
A semiconductor device includes a substrate having a peripheral region and a cell region therein. A first semiconductor active pattern is provided, which protrudes from the substrate in the peripheral region. A second semiconductor active pattern is provided, which protrudes from the substrate in the cell region. A first edge of an upper portion of the first semiconductor active pattern has a rounded shape, and a second edge of an upper portion of the second semiconductor active pattern has a rounded shape. A curvature of the first edge is greater than a curvature of the second edge.
1 . A semiconductor device, comprising:
a substrate having a peripheral region including peripheral circuits and a cell region including memory integrated circuits;
a first active pattern protruding from the substrate, in the peripheral region;
a second active pattern protruding from the substrate, in the cell region; and
a device isolation pattern being located in the peripheral region and extending adjacent to a sidewall of the first active pattern,
wherein a first edge of an upper portion of the first active pattern has a rounded shape, and a second edge of an upper portion of the second active pattern has a rounded shape,
wherein a curvature of the first edge is greater than a curvature of the second edge,
wherein a top surface of the device isolation pattern is located at a height that is lower than a top surface of the first active pattern, and
wherein the top surface of the device isolation pattern is concavely recessed toward an inside of the device isolation pattern.
2 . The semiconductor device of claim 1 , wherein the first active pattern has: (i) a first cross-sectional width at a base thereof, which extends adjacent the substrate, (ii) a second cross-sectional width adjacent the top surface thereof, and (iii) a third cross-sectional width at a midpoint intermediate the substrate and the top surface; and wherein the first cross-sectional width is greater than the third cross-sectional width, which is greater than the second cross-sectional width.
3 . The semiconductor device of claim 2 , wherein a difference between the third cross-sectional width and the first cross-sectional width is less than a difference between the third cross-sectional width and the second cross-sectional width.
4 . The semiconductor device of claim 1 , wherein a width of the top surface of the first active pattern is greater than a width of a top surface of the second active pattern.
5 . The semiconductor device of claim 1 , wherein, as measured at a bottom level of the first active pattern, an angle between a top surface of the substrate and a side surface of the first active pattern is greater than 90°.
6 . The semiconductor device of claim 1 ,
wherein the device isolation pattern has a seam therein.
7 . The semiconductor device of claim 6 , wherein a height of a top portion of the seam, as measured relative to the substrate, is less than a height of the device isolation pattern.
8 . The semiconductor device of claim 1 , further comprising:
a gate dielectric pattern extended along the top surface of the first active pattern and the top surface of the device isolation pattern,
wherein a bottom surface of the gate dielectric pattern has a rounded shape that corresponds to the first edge of the upper portion of the first active pattern.
9 . The semiconductor device of claim 8 , wherein a radius of curvature along the rounded shape of the bottom surface of the gate dielectric pattern corresponds to a radius of curvature along the first edge of the upper portion of the first active pattern.
10 . A semiconductor device, comprising:
a substrate having a peripheral region including peripheral circuits, and a cell region including memory integrated circuits;
an active pattern protruding from the substrate, within the peripheral region;
a device isolation pattern provided between the active pattern and an adjacent active pattern; and
a gate dielectric pattern extended along a top surface of the active pattern and along a top surface of the device isolation pattern,
wherein an edge of an upper portion of the active pattern has a rounded shape,
wherein the top surface of the device isolation pattern is located at a height that is lower than the top surface of the active pattern,
wherein the top surface of the device isolation pattern is concavely recessed toward an inside of the device isolation pattern, and
wherein a bottom surface of the gate dielectric pattern has a rounded shape corresponding to the edge of the upper portion of the active pattern.
11 . The semiconductor device of claim 10 , wherein, at a bottom level of the active pattern, a first angle between a top surface of the substrate and a side surface of the active pattern is greater than 90°.
12 . The semiconductor device of claim 10 , wherein the device isolation pattern includes a seam provided therein.
13 . The semiconductor device of claim 12 , wherein a top portion of the seam is located at a height lower than the top surface of the device isolation pattern.
14 . The semiconductor device of claim 10 , wherein the gate dielectric pattern has a non-zero curvature at a region adjacent to the edge of the upper portion of the active pattern.
15 . A semiconductor device, comprising:
a substrate having a peripheral region including peripheral circuits, and a cell region including memory integrated circuits;
a first active pattern protruding from the substrate, in the peripheral region;
a second active pattern protruding from the substrate, in the cell region; and
a device isolation pattern provided between the first active pattern and an adjacent active pattern,
wherein a first edge of an upper portion of the first active pattern has a rounded shape, and a second edge of an upper portion of the second active pattern has a rounded shape,
wherein the rounded shape of the first edge is convex, and the rounded shape of the second edge is convex,
wherein a radius of curvature of the first edge is less than a radius of curvature of the second edge,
wherein a top surface of the device isolation pattern is located at a height that is lower than a top surface of the first active pattern, and
wherein the top surface of the device isolation pattern is concavely recessed toward an inside of the device isolation pattern.
16 . The semiconductor device of claim 15 , wherein
the first active pattern has: (i) a first cross-sectional width at a base thereof, which extends adjacent the substrate, (ii) a second cross-sectional width adjacent a top surface thereof, and (iii) a third cross-sectional width at a midpoint intermediate the substrate and the top surface,
wherein the first cross-sectional width is greater than the third cross-sectional width, which is greater than the second cross-sectional width, and
wherein a difference between the third cross-sectional width and the first cross-sectional width is less than a difference between the third cross-sectional width and the second cross-sectional width.
17 . The semiconductor device of claim 16 , further comprising:
a gate dielectric pattern extended along the top surface of the first active pattern and along a top surface of the device isolation pattern,
wherein a bottom surface of the gate dielectric pattern has a rounded shape corresponding to the first edge.
18 . The semiconductor device of claim 15 , wherein the second edge is more convex than the first edge.