Semiconductor structure and method for forming the same
A semiconductor structure includes an active region of a substrate, a gate electrode layer disposed over the active region, an isolation structure surrounding the active region and the gate electrode layer, and a gate dielectric layer. The gate dielectric layer includes a first portion interposed between the bottom surface of the gate electrode layer and the top surface of the active region. The gate dielectric layer also includes a second portion interposed between the isolation structure and the sidewall of the active region.
1 . A semiconductor structure, comprising:
an active region over a substrate;
a gate electrode layer disposed over the active region;
an isolation structure surrounding the active region and the gate electrode layer; and
a gate dielectric layer comprising a first portion interposed between a bottom surface of the gate electrode layer and a top surface of the active region, wherein the active region has an outermost sidewall that extends continuously downward from an end of the top surface of the active region to a top surface of the substrate, and the gate dielectric layer further comprises a second portion interposed between the isolation structure and the outermost sidewall of the active region.
2 . The semiconductor structure as claimed in claim 1 , wherein the gate dielectric layer further comprises a third portion interposed between the isolation structure and a sidewall of the gate electrode layer.
3 . The semiconductor structure as claimed in claim 1 , wherein the isolation structure comprises a first insulating material and a first lining layer lining between the first insulating material and the outermost sidewall of the active region, and a top surface of the first lining layer is located lower than the top surface of the active region.
4 . The semiconductor structure as claimed in claim 3 , wherein the second portion of the gate dielectric layer partially abuts the first lining layer of the isolation structure.
5 . The semiconductor structure as claimed in claim 3 , wherein the first lining layer of the isolation structure extends between the second portion of the gate dielectric layer and the outermost sidewall of the active region.
6 . The semiconductor structure as claimed in claim 3 , wherein the isolation structure further comprises a second lining layer lining between the first insulating material and the first lining layer, the second lining layer and the first lining layer are made of different materials, and the second portion of the gate dielectric layer partially abuts the second lining layer of the isolation structure.
7 . The semiconductor structure as claimed in claim 3 , wherein the isolation structure further comprises a second insulating material disposed over the first insulating material, wherein the second portion of the gate dielectric layer has a bottom surface that is located not lower than an interface between the second insulating material and the first insulating material.
8 . The semiconductor structure as claimed in claim 1 , wherein the bottom surface of the gate electrode layer meets with a sidewall of the gate electrode layer at an obtuse angle.
9 . The semiconductor structure as claimed in claim 1 , wherein a thickness of the first portion of the gate dielectric layer is less than a width of the second portion of the gate dielectric layer.
10 . The semiconductor structure as claimed in claim 1 , wherein the gate dielectric layer is configured as a tunnel oxide layer of a flash memory, and the gate electrode layer is configured as a floating gate of the flash memory.