Three-dimensional NAND memory device with improved leakage current and fabrication method
A method of forming a three-dimensional (3D) NAND memory device includes: forming a gate line slit through alternating layers of an oxide layer and a conductive material layer, wherein the conductive material layer is further formed on a sidewall and a bottom of the gate line slit; performing a first etch process to remove portions of the conductive material layer from the sidewall and the bottom of the gate line slit and from between adjacent oxide layers, thereby exposing portions of the oxide layer in the gate line slit; removing the exposed portions of the oxide layer on the sidewall of the gate line slit; and performing a second etch process to remove residues of the conductive material layer in the gate line slit.
1 . A three-dimensional (3D) NAND memory device, comprising:
alternating layers of an oxide layer and a conductive material layer formed on a semiconductor layer;
memory cells formed in the alternating layers of the oxide layer and the conductive material layer; and
a plurality of gate line slit structures formed through the alternating layers to separate the memory cells into blocks,
wherein the oxide layer of the alternating layers comprises:
a first portion in contact with a dielectric material layer that is disposed between the oxide layer and an adjacent conductive material layer, and
a second portion in contact with a gate line slit structure of the plurality of gate line slit structures, wherein
the dielectric material layer and the adjacent conductive material layer each have a sidewall recessed from a sidewall of the second portion of the oxide layer adjacent to the gate line slit structure, and
the dielectric material layer disposed between the oxide layer and the adjacent conductive material layer is a composite layer comprising a high-K material sub-layer and a TiN material sub-layer.
2 . The 3D NAND memory device according to claim 1 , further comprising:
channel holes formed in the alternating layers, each channel hole comprising a functional layer and a channel layer.
3 . The 3D NAND memory device according to claim 1 , wherein:
the dielectric material layer disposed between the oxide layer and the adjacent conductive material layer comprises a high-K material layer,
wherein the high-K material layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon, titanium oxide, titanium nitride, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or a combination thereof.
4 . The 3D NAND memory device according to claim 1 , wherein:
another conductive material layer is disposed at a bottom and a lower portion of the gate line slit structure and is physically isolated from any conductive material layer of the alternating layers.
5 . The 3D NAND memory device according to claim 4 , wherein:
a recessed area is formed between adjacent oxide layers of the alternating layers, and on the sidewalls of the dielectric material layer and the adjacent conductive material layer, and
the gate line slit structure is further formed into the recessed area.
6 . The 3D NAND memory device according to claim 5 , further comprising:
a spacer layer on the sidewall of the second portion of the oxide layer, in the recessed area, and on the another conductive material layer at a bottom of the gate line slit structure.
7 . The 3D NAND memory device according to claim 4 , further comprising:
a spacer layer on the sidewall of the second portion of the oxide layer and on the another conductive material layer at a bottom of the gate line slit structure.
8 . The 3D NAND memory device according to claim 1 , wherein:
a recessed area is formed between adjacent oxide layers of the alternating layers, and on the sidewalls of the dielectric material layer and the adjacent conductive material layer, and
the gate line slit structure is further formed into the recessed area.
9 . The 3D NAND memory device according to claim 1 , further comprising:
a spacer layer on the sidewall of the second portion of the oxide layer and a bottom of the gate line slit structure.
10 . A memory system, comprising:
a three-dimensional (3D) NAND memory device; and
a memory controller coupled to the 3D NAND memory device and configured to control operations of the 3D NAND memory device,
wherein the 3D NAND memory device includes:
alternating layers of an oxide layer and a conductive material layer formed on a semiconductor layer;
memory cells formed in the alternating layers of the oxide layer and the conductive material layer; and
a plurality of gate line slit structures formed through the alternating layers to separate the memory cells into blocks, wherein the oxide layer of the alternating layers comprises:
a first portion in contact with a dielectric material layer that is disposed between the oxide layer and an adjacent conductive material layer, and
a second portion in contact with a gate line slit structure of the plurality of gate line slit structures, wherein
the dielectric material layer and the adjacent conductive material layer each have a sidewall recessed from a sidewall of the second portion of the oxide layer adjacent to the gate line slit structure, and
the dielectric material layer disposed between the oxide layer and the adjacent conductive material layer is a composite layer comprising a high-K material sub-layer and a TiN material sub-layer.
11 . The memory system according to claim 10 , wherein:
the 3D NAND memory device further comprises channel holes formed in the alternating layers, each channel hole comprising a functional layer and a channel layer.
12 . The memory system according to claim 10 , wherein:
another conductive material layer is disposed at a bottom and a lower portion of the gate line slit structure and is physically isolated from any conductive material layer of the alternating layers.
13 . The memory system according to claim 12 , further comprising:
a spacer layer on the sidewall of the second portion of the oxide layer and on the another conductive material layer at a bottom of the gate line slit structure.
14 . The memory system according to claim 13 , wherein:
the spacer layer is further in a recessed area that is formed between adjacent oxide layers of the alternating layers, and on the sidewalls of the dielectric material layer and the adjacent conductive material layer.
15 . The memory system according to claim 10 , wherein:
a recessed area is formed between adjacent oxide layers of the alternating layers, and on the sidewalls of the dielectric material layer and the adjacent conductive material layer, and
the gate line slit structure is further formed into the recessed area.
16 . The memory system according to claim 10 , further comprising:
a spacer layer on the sidewall of the second portion of the oxide layer and a bottom of the gate line slit structure.