Microelectronic devices including a doped dielectric material, methods of forming the microelectronic devices, and related systems
A microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. The doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. Conductive contact structures are in the doped dielectric material. Additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.
1 . A microelectronic device, comprising:
tiers of alternating dielectric materials and conductive materials;
a cap dielectric material adjacent to the tiers;
pillars extending through the tiers;
a doped dielectric material vertically adjacent to the tiers and the cap dielectric material, the doped dielectric material comprising a heterogeneous chemical composition comprising one or more dopants; and
conductive contact structures in the doped dielectric material.
2 . The microelectronic device of claim 1 , wherein the doped dielectric material comprises a gradient of the one or more dopants.
3 . The microelectronic device of claim 1 , wherein the doped dielectric material comprises regions, one or more of the regions comprising a different concentration of the one or more dopants relative to other of the one or more regions.
4 . The microelectronic device of claim 1 , wherein the doped dielectric material comprises two or more regions, one of the two or more regions comprising a different concentration gradient of the one or more dopants relative to other of the two or more regions.
5 . The microelectronic device of claim 1 , wherein a lower region of the doped dielectric material comprises a relatively lower concentration of the one or more dopants than an upper region of the doped dielectric material.
6 . The microelectronic device of claim 1 , wherein a lower region of the doped dielectric material comprises a relatively higher concentration of the one or more dopants than an upper region of the doped dielectric material.
7 . The microelectronic device of claim 1 , wherein the doped dielectric material comprises doped silicon oxide.
8 . The microelectronic device of claim 1 , wherein the one or more dopants comprises phosphorous, boron, carbon, nitrogen, or a combination thereof.
9 . The microelectronic device of claim 1 , wherein a lower region of the doped dielectric material comprises a first concentration of the dopant and an upper region of the doped dielectric material comprises a second, different concentration of the dopant.
10 . The microelectronic device of claim 1 , wherein a lower region of the doped dielectric material comprises a first dopant and an upper region of the doped dielectric material comprises a second, different dopant.
11 . The microelectronic device of claim 10 , wherein the lower region of the doped dielectric material comprises a gradient of the first dopant and the upper region of the doped dielectric material comprises a gradient of the second dopant.
12 . A microelectronic device, comprising:
tiers of alternating dielectric materials and conductive materials;
pillars extending through the tiers;
a doped dielectric material vertically adjacent to the tiers, the doped dielectric material comprising two or more dopants heterogeneously distributed therein;
an oxide material between the tiers and the doped dielectric material; and
conductive contact structures in the doped dielectric material vertically adjacent to the pillars, a critical dimension of the conductive contact structures less than a critical dimension of the pillars.
13 . The microelectronic device of claim 12 , wherein the conductive contact structures exhibit substantially vertical sidewalls.
14 . The microelectronic device of claim 12 , wherein the conductive contact structures exhibit tapered sidewalls.
15 . The microelectronic device of claim 12 , wherein the doped dielectric material comprises discrete regions and one of the discrete regions comprises a relative greater concentration of the two or more dopants than another of the discrete regions.
16 . The microelectronic device of claim 12 , wherein the doped dielectric material comprises a gradient of the two or more dopants.
17 . A microelectronic system, comprising:
an input device;
an output device;
a processor device operably coupled to the input device and the output device; and
memory devices operably coupled to the processor device, one or more of the memory devices comprising:
memory pillars extending vertically through tiers of alternating oxide materials and conductive materials; and
a doped dielectric material over the memory pillars, the doped dielectric material comprising a varying dopant concentration along a height of the doped dielectric material.
18 . The microelectronic system of claim 17 , wherein the dopant concentration of the doped dielectric material is relatively higher proximal to the tiers.
19 . The microelectronic system of claim 17 , further comprising a cap dielectric material and a barrier material between the tiers and the doped dielectric material, the doped dielectric material direct contacting the barrier material and the cap dielectric material direct contacting the barrier material.
20 . A method of forming a microelectronic device, comprising:
forming tiers of alternating conductive materials and dielectric materials and pillars extending vertically through the tiers;
forming a cap dielectric material adjacent to the tiers;
forming a doped dielectric material vertically adjacent to the tiers and the cap dielectric material, the doped dielectric material comprising a heterogeneous chemical composition and formulated to exhibit different etch rates at different portions of the doped dielectric material;
removing a portion of the doped dielectric material to form openings in the doped dielectric material;
removing an additional portion of the doped dielectric material to increase a width of the openings in the doped dielectric material; and
forming conductive contact structures in the openings, a critical dimension of the conductive contact structures relatively less than or equal to a critical dimension of the pillars.
21 . The method of claim 20 , wherein forming a doped dielectric material adjacent to the tiers comprises forming the doped dielectric material comprising a greater dopant concentration proximal to the tiers.
22 . The method of claim 21 , wherein removing a portion of the doped dielectric material to form openings and removing an additional portion of the doped dielectric material to increase a width of the openings comprises removing the portion of the doped dielectric material at a faster etch rate than removing the additional portion of the doped dielectric material.
23 . The method of claim 20 , wherein forming a doped dielectric material adjacent to the tiers comprises forming the doped dielectric material comprising a gradient of one or more dopants.
24 . The method of claim 20 , wherein removing a portion of the doped dielectric material to form openings comprises removing the portion using a dry etch process.
25 . The method of claim 20 , wherein removing a portion of the doped dielectric material to form openings comprises removing the portion using a wet etch process.