Semiconductor memory device and manufacturing method of the semiconductor memory device

1 . A semiconductor memory device, comprising:

a source stack and a preliminary source stack spaced apart from each other;

a conductive contact plug passing through the source stack;

a charge dispersion layer passing through a portion of the preliminary source stack;

a dummy stack including dummy insulating layers and sacrificial insulating layers stacked alternately with each other over the preliminary source stack;

a lower peripheral contact plug passing through the preliminary source stack; and

an upper peripheral contact plug passing through the dummy stack and overlapping the lower peripheral contact plug.

2 . The semiconductor memory device of claim 1 ,

wherein the conductive contact plug passes through a bottom surface of the source stack, and

a portion of the preliminary source stack extends along a bottom surface of the charge dispersion layer.

3 . The semiconductor memory device of claim 1 ,

wherein a width of the charge dispersion layer is less than a width of the conductive contact plug.

4 . The semiconductor memory device of claim 1 , further comprising a support passing through at least one of the preliminary source stack and the dummy stack.

5 . The semiconductor memory device of claim 1 ,

wherein the preliminary source stack includes a first source layer and a second source layer on the first source layer, and

wherein the charge dispersion layer passes through a portion of the first source layer.

6 . The semiconductor memory device of claim 5 , wherein the charge dispersion layer comprises:

a bottom surface contacting the first source layer; and

a sidewall contacting the second source layer.

7 . The semiconductor memory device of claim 1 , further comprising:

isolation layers arranged in a substrate;

a peripheral circuit structure including a transistor arranged over a first active area overlapped by the preliminary source stack, among active regions of the substrate separated from each other by the isolation layers; and

a lower insulation structure covering the peripheral circuit structure between the substrate and the preliminary source stack.

8 . The semiconductor memory device of claim 1 , further comprising:

isolation layers arranged in a substrate;

a discharge impurity region defined in a second active region overlapped by the conductive contact plug among active regions of the substrate separated from each other by the isolation layers, the discharge impurity region contacting the conductive contact plug; and

a lower insulation structure arranged between the substrate and the source stack and penetrated by the conductive contact plug.

9 . The semiconductor memory device of claim 1 , further comprising:

a cell stack including cell interlayer insulating layers and conductive patterns stacked alternately with each other over the source stack; and

a channel structure passing through the cell stack and coupled to the source stack.

10 . The semiconductor memory device of claim 9 ,

wherein the channel structure extends into the source stack and has a sidewall directly contacting the source stack.

11 . The semiconductor memory device of claim 1 ,

wherein the conductive contact plug is spaced apart from the charge dispersion layer.