Nonvolatile memory device

1 . A nonvolatile memory device comprising:

a substrate including a cell array region and an extension region;

a plurality of gate electrodes stacked on the substrate, the plurality of gate electrodes comprising at least one first gate electrode and a plurality of second gate electrodes stacked on the at least one first gate electrode, the at least one first gate electrode including a first opening on the cell array region and a second opening on the extension region;

a word line cutting region cutting the plurality of gate electrodes and extending in a first direction that is parallel with an upper surface of the substrate; and

a plurality of channel structures passing through the plurality of gate electrodes.

2 . The nonvolatile memory device of claim 1 , wherein at least a portion of the first opening overlaps the second opening in the first direction.

3 . The nonvolatile memory device of claim 1 , wherein at least a portion of the word line cutting region overlaps the first opening in the first direction.

4 . The nonvolatile memory device of claim 1 , wherein at least a portion of the word line cutting region overlaps the second opening in the first direction.

5 . The nonvolatile memory device of claim 1 , wherein the word line cutting region has a first width in a second direction intersecting with the first direction,

wherein the first opening has a second width in the second direction, and

wherein the first width is smaller than the second width.

6 . The nonvolatile memory device of claim 1 , wherein the plurality of channel structures are spaced apart from the first opening.

7 . The nonvolatile memory device of claim 1 , wherein the word line cutting region does not cut the plurality of channel structures.

8 . The nonvolatile memory device of claim 1 , wherein the word line cutting region is disposed at a center of the first opening.

9 . The nonvolatile memory device of claim 1 , wherein the at least one first gate electrode is a ground select line.

10 . A nonvolatile memory device comprising:

a substrate;

at least one first gate electrode including an opening on the substrate;

a plurality of second gate electrodes stacked on the at least one first gate electrode and including convex portions having an outward curve extending toward the substrate;

a first channel structure passing through the at least one first gate electrode and the plurality of second gate electrodes; and

a second channel structure passing through the at least one first gate electrode and the plurality of second gate electrodes and spaced apart from the first channel structure in a first direction,

wherein the convex portions of the plurality of second gate electrodes and the opening of the at least one first gate electrode are formed between the first channel structure and the second channel structure.

11 . The nonvolatile memory device of claim 10 , wherein at least a portion of the convex portions of the plurality of second gate electrodes overlaps the opening of the at least one first gate electrode.

12 . The nonvolatile memory device of claim 10 , further comprising:

a plurality of third gate electrodes stacked on the substrate, the plurality of third gate electrodes being between the substrate and the at least one first gate electrode,

wherein the plurality of third gate electrodes do not include convex portions.

13 . The nonvolatile memory device of claim 10 , further comprising:

a plurality of third gate electrodes stacked on the plurality of second gate electrodes,

wherein the plurality of second gate electrodes are between the at least one first gate electrode and the plurality of third gate electrodes, and

wherein the plurality of third gate electrodes do not include convex portions.

14 . The nonvolatile memory device of claim 10 , wherein the convex portion included in one of the plurality of second gate electrodes has a first width in the first direction,

wherein the convex portion included in another of the plurality of second gate electrodes has a second width in the first direction, and

wherein the first width is different from the second width.

15 . The nonvolatile memory device of claim 10 , wherein the opening has a first width in the first direction,

wherein the convex portion included in one of the plurality of second gate electrodes, which is adjacent to the at least one first gate electrode, has a second width in the first direction, and

wherein the first width is smaller than the second width.

16 . The nonvolatile memory device of claim 10 , further comprising:

a word line cutting region cutting the opening and the convex portions.

17 . The nonvolatile memory device of claim 16 , wherein the word line cutting region does not cut the first channel structure and the second channel structure.

18 . A nonvolatile memory device comprising:

a substrate including a cell array region and an extension region;

a mold structure including a plurality of gate electrodes and a plurality of insulating films alternately stacked on the substrate; and

a plurality of channel structures passing through the mold structure,

wherein the plurality of gate electrodes includes at least one first gate electrode and a plurality of second gate electrodes stacked on the at least one first gate electrode,

wherein the at least one first gate electrode includes a first opening on the cell array region and a second opening on the extension region,

wherein one of the plurality of insulating films is between the at least one first gate electrode and one of the plurality of second gate electrodes adjacent to the at least one first gate electrode to fill the first opening and the second opening, and

wherein at least a portion of the first opening overlaps the second opening in a first direction that is parallel with an upper surface of the substrate.

19 . The nonvolatile memory device of claim 18 , further comprising:

a source plate between the substrate and the mold structure,

wherein each of the plurality of channel structures includes a channel film, and

wherein the channel film is electrically connected to the source plate.

20 . The nonvolatile memory device of claim 18 , wherein the plurality of channel structures are not formed on the first opening and the second opening.