Semiconductor memory device, method for fabricating the same and electronic system including the same
A semiconductor memory device includes a cell substrate including a first surface and a second surface opposite to the first surface, a first mold stack including a plurality of first gate electrodes sequentially stacked on the first surface, a second mold stack including a plurality of second gate electrodes sequentially stacked on the first mold stack, a first channel structure extending in a first direction with respect to the first surface and crossing the plurality of first gate electrodes and the plurality of second gate electrodes, and an input/output pad on the second surface, wherein the first mold stack includes a mold opening that exposes a portion of the second mold stack, and at least a portion of the input/output pad overlaps the mold opening in the first direction.
1 . A semiconductor memory device comprising:
a cell substrate including a first surface and a second surface opposite to the first surface;
a first mold stack including a plurality of first gate electrodes sequentially stacked on the first surface;
a second mold stack including a plurality of second gate electrodes sequentially stacked on the first mold stack;
a first channel structure extending in a first direction crossing the first surface and crossing the plurality of first gate electrodes and the plurality of second gate electrodes; and
an input/output pad on the second surface,
wherein the first mold stack includes a mold opening that exposes a portion of the second mold stack, and
at least a portion of the input/output pad overlaps the mold opening in the first direction.
2 . The semiconductor memory device of claim 1 , wherein the cell substrate includes a substrate opening that exposes at least a portion of the mold opening, and
at least a portion of the input/output pad overlaps the substrate opening in the first direction.
3 . The semiconductor memory device of claim 1 , wherein one end of the first channel structure is electrically connected to the cell substrate.
4 . The semiconductor memory device of claim 3 , wherein the cell substrate includes polysilicon (poly-Si) doped with impurities.
5 . The semiconductor memory device of claim 1 , further comprising a second channel structure extending in the first direction to pass through the mold opening, crossing the plurality of second gate electrodes.
6 . The semiconductor memory device of claim 1 , further comprising:
a cell wiring structure spaced apart from the cell substrate with the first and second mold stacks therebetween; and
a contact plug extending in the first direction and electrically connecting the input/output pad with the cell wiring structure.
7 . The semiconductor memory device of claim 6 , wherein the contact plug does not overlap the mold opening in the first direction.
8 . The semiconductor memory device of claim 6 , wherein the contact plug passes through the mold opening and the second mold stack.
9 . The semiconductor memory device of claim 1 , wherein the first channel structure has a step difference at a boundary between the first mold stack and the second mold stack.
10 . The semiconductor memory device of claim 1 , further comprising a support stack including a mold insulating layer and a mold sacrificial layer, which are alternately stacked, in the mold opening.
11 . The semiconductor memory device of claim 10 , wherein the support stack is spaced apart from the plurality of first gate electrodes in a second direction crossing the first direction.
12 . A semiconductor memory device comprising:
a peripheral circuit structure; and
a cell structure stacked on the peripheral circuit structure,
wherein the cell structure includes:
a cell substrate including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface;
a first mold stack and a second mold stack, which are sequentially stacked on the first surface, each of the first mold stack and the second mold stack including a plurality of gate electrodes;
a first channel structure extending in a first direction crossing the first surface and passing through the first mold stack and the second mold stack;
an input/output pad on the second surface; and
a contact plug extending in the first direction to electrically connect the peripheral circuit structure with the input/output pad,
wherein the first mold stack includes a mold opening that exposes a portion of the second mold stack, and
wherein at least a portion of the input/output pad overlaps the mold opening in the first direction.
13 . The semiconductor memory device of claim 12 , wherein the cell substrate includes a substrate opening that exposes at least a portion of the mold opening, and
at least a portion of the input/output pad overlaps the substrate opening in the first direction.
14 . The semiconductor memory device of claim 12 , further comprising a filling material layer in the first mold stack and in the mold opening.
15 . The semiconductor memory device of claim 14 , further comprising a second channel structure extending in the first direction to pass through the filling material layer and the second mold stack.
16 . The semiconductor memory device of claim 12 , further comprising an insulating spacer on sides of the contact plug.
17 . The semiconductor memory device of claim 12 , wherein the cell structure further includes:
a word line cutting region extending in a first direction crossing the first direction to cut the first mold stack and the second mold stack;
a bit line extending in a second direction crossing the first direction and the first direction and electrically connected to the first channel structure; and
a cell wiring structure electrically connected to the plurality of gate electrodes, the bit line and the contact plug.
18 . The semiconductor memory device of claim 17 , wherein the peripheral circuit structure includes:
a peripheral circuit substrate facing the first surface;
a peripheral circuit element on the peripheral circuit substrate; and
a peripheral circuit wiring structure electrically connected to the peripheral circuit element and bonded to the cell wiring structure.
19 . An electronic system comprising:
a main board;
a semiconductor memory device including a peripheral circuit structure and a cell structure, which are sequentially stacked, on the main board; and
a controller electrically connected with the semiconductor memory device on the main board,
wherein the cell structure includes:
a cell substrate including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface,
a first mold stack and a second mold stack, which are sequentially stacked on the first surface, each of the first mold stack and the second mold stack including a plurality of gate electrodes,
a first channel structure extending in a first direction crossing the first surface and passing through the first mold stack and the second mold stack, and
an input/output pad electrically connected with the controller on the second surface,
wherein the first mold stack includes a mold opening that exposes a portion of the second mold stack, and
at least a portion of the input/output pad overlaps the mold opening in the first direction.
20 . The electronic system of claim 19 , wherein the input/output pad is electrically connected to the controller through a bonding wire.