Three-dimensional memory device containing silicon oxycarbide liners and methods of forming the same

1 . A memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers, wherein a first electrically conductive layer of the electrically conductive layers has a first major horizontal surface in contact with a silicon oxycarbide liner and an opposing second major surface in contact with one of the insulating layers or with a dielectric material layer composed of a silicon oxide material;

a memory opening vertically extending through the alternating stack;

a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film, wherein the memory film comprises, from outside to inside, a dielectric metal oxide blocking dielectric layer, a silicon oxide blocking dielectric layer, a continuous memory material layer, and a tunneling dielectric layer;

a vertical stack of tubular silicon oxide spacers that are vertically spaced apart from each other, and laterally surrounding and contacting the dielectric metal oxide blocking dielectric layer; and

divot-fill annular dielectric spacers contacting a concave tapered surface of a respective one of the tubular silicon oxide spacers and contacting a respective cylindrical surface segment of an outer sidewall of the dielectric metal oxide blocking dielectric layer.

2 . The memory device of claim 1 , further comprising an annular silicon oxide spacer having an inner sidewall contacting a cylindrical surface segment of an outer sidewall of the dielectric metal oxide blocking dielectric layer and having a concave and tapered outer sidewall segment contacting a first convex and tapered annular surface segment of the first electrically conductive layer,

wherein:

one of the divot-fill annular dielectric spacers contacts a second convex and tapered annular surface segment of the first electrically conductive layer; and

wherein the annular silicon oxide spacer has a planar annular bottom surface contacting an annular segment of a top surface of a horizontally-extending portion of the dielectric metal oxide blocking dielectric layer.

3 . The memory device of claim 1 , wherein:

one of the tubular silicon oxide spacers comprises a concave and tapered outer sidewall segment contacting a first convex and tapered annular surface segment of the first electrically conductive layer; and

one of the divot-fill annular dielectric spacers contacts a second convex and tapered annular surface segment of the first electrically conductive layer.

4 . The memory device of claim 1 , wherein a sidewall surface and a peripheral portion of a horizontal planar surface of the silicon oxycarbide liner is in contact with one of the divot-fill annular dielectric spacers.

5 . A memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers, wherein a first electrically conductive layer of the electrically conductive layers has a first major horizontal surface in contact with a silicon oxycarbide liner and an opposing second major surface in contact with one of the insulating layers or with a dielectric material layer composed of a silicon oxide material;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film;

wherein:

the first electrically conductive layer comprises a horizontally-extending planar surface that contacts the silicon oxycarbide liner;

the first electrically conductive layer comprises a first convex and tapered annular surface segment having a first radius of curvature, and a second convex and tapered annular surface segment having a second radius of curvature that is less than the first radius of curvature; and

an edge of the second convex and tapered annular surface segment is adjoined to an edge of the horizontally-extending planar surface.

6 . A memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers, wherein a first electrically conductive layer of the electrically conductive layers has a first major horizontal surface in contact with a silicon oxycarbide liner and an opposing second major surface in contact with one of the insulating layers or with a dielectric material layer composed of a silicon oxide material;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film;

wherein:

the alternating stack comprises a first tier, a second tier and the dielectric material layer composed of the silicon oxide material is located between the first tier and the second tier;

the first tier comprises alternating first electrically conductive layers and first insulating layers, lower silicon oxycarbide liners located between lower major horizontal surfaces of the first electrically conductive layers and upper major horizontal surfaces of the underlying first insulating layers, and upper silicon oxycarbide liners located between upper major horizontal surfaces of a subset of the first electrically conductive layers and lower major horizontal surfaces of the overlying first insulating layers, wherein the upper silicon oxycarbide liner is not located on the upper major horizontal surface topmost one of the first electrically conductive layers; and

the second tier comprises alternating second electrically conductive layers and second insulating layers, upper silicon oxycarbide liners located between upper major horizontal surfaces of the second electrically conductive layers and lower major horizontal surfaces of the overlying second insulating layers, and lower silicon oxycarbide liners located between lower major horizontal surfaces of a subset the second electrically conductive layers and upper major horizontal surfaces of the underlying second insulating layers, wherein the lower silicon oxycarbide liner is not located on the lower major horizontal surface of a bottommost one of the second electrically conductive layers.

7 . A memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers, wherein each of the electrically conductive layers is vertically spaced from a respective overlying insulating layer and from a respective underlying insulating layer by a respective backside dielectric metal oxide blocking dielectric layer, wherein a first backside dielectric metal oxide blocking dielectric layer of the backside dielectric metal oxide blocking dielectric layers comprises a first horizontal surface that is in direct contact with a silicon oxycarbide liner and a second horizontal surface that is in direct contact with one of the insulating layers or a dielectric material layer composed of a silicon oxide material;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a memory film.

8 . The memory device of claim 7 , wherein:

the first backside dielectric metal oxide blocking dielectric layer embeds a first electrically conductive layer of the electrically conductive layers; and

the second horizontal surface is vertically spaced from the first horizontal surface by a sum of a vertical thickness of the first electrically conductive layer and twice a thickness of the first backside dielectric metal oxide blocking dielectric layer.

9 . The memory device of claim 7 , wherein:

the memory film comprises, from outside to inside, a silicon oxide blocking dielectric layer, a continuous memory material layer, and a tunneling dielectric layer; and

the silicon oxide blocking dielectric layer is in contact with each of the backside dielectric metal oxide blocking dielectric layers.

10 . The memory device of claim 9 , wherein:

the second horizontal surface of the first backside dielectric metal oxide blocking dielectric layer is in direct contact with a horizontal planar surface of the silicon oxide blocking dielectric layer;

the silicon oxide blocking dielectric layer comprises an outer sidewall having a vertical stack of annular lateral indentations that are vertically spaced apart; and

each of the annular lateral indentations comprises a cylindrical surface segment and a pair of annular concave surface segment adjoined to a respective edge of the cylindrical surface segment.

11 . The memory device of claim 10 , further comprising divot-fill annular dielectric spacers contacting a respective annular concave surface segment of the annular lateral indentations of the silicon oxide blocking dielectric layer, wherein:

the first backside dielectric metal oxide blocking dielectric layer comprises a first convex and tapered annular surface segment having a first radius of curvature and contacting an annular concave surface segment of the silicon oxide blocking dielectric layer, and a second convex and tapered annular surface segment having a second radius of curvature that is less than the first radius of curvature and contacting one of the divot-fill annular dielectric spacers.

12 . The memory device of claim 9 , wherein:

the alternating stack comprises a first tier, a second tier and the dielectric material layer composed of the silicon oxide material is located between the first tier and the second tier;

the first tier comprises alternating first electrically conductive layers and first insulating layers, lower silicon oxycarbide liners located between lower major horizontal surfaces of the first electrically conductive layers and upper major horizontal surfaces of the underlying first insulating layers, and upper silicon oxycarbide liners located between upper major horizontal surfaces of a subset of the first electrically conductive layers and lower major horizontal surfaces of the overlying first insulating layers, wherein the upper silicon oxycarbide liner is not located on the upper major horizontal surface topmost one of the first electrically conductive layers; and

the second tier comprises alternating second electrically conductive layers and second insulating layers, upper silicon oxycarbide liners located between upper major horizontal surfaces of the second electrically conductive layers and lower major horizontal surfaces of the overlying second insulating layers, and lower silicon oxycarbide liners located between lower major horizontal surfaces of a subset the second electrically conductive layers and upper major horizontal surfaces of the underlying second insulating layers, wherein the lower silicon oxycarbide liner is not located on the lower major horizontal surface of a bottommost one of the second electrically conductive layers.