Three-dimensional semiconductor memory device and electronic system including the same
The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a peripheral circuit structure on a peripheral substrate, a stack structure that includes a plurality of gate electrodes stacked on the peripheral circuit structure, an n-doped pattern on the stack structure, a vertical structure that extends through the stack structure into the n-doped pattern, a p-doped pattern on the n-doped pattern, and an undoped pattern between the n-doped pattern and then p-doped pattern. The p-doped pattern includes a p-doped horizontal pattern on the undoped pattern, and a p-doped vertical pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure.
1 . A three-dimensional semiconductor memory device comprising:
a circuit structure on a substrate;
a stack structure that includes a plurality of gate electrodes stacked on the circuit structure;
an n-doped pattern on the stack structure;
a vertical structure that extends through the stack structure into the n-doped pattern;
a p-doped pattern on the n-doped pattern; and
an undoped pattern between the n-doped pattern and then p-doped pattern,
wherein the p-doped pattern includes:
a p-doped horizontal pattern on the undoped pattern; and
a p-doped vertical pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure.
2 . The device of claim 1 , wherein the undoped pattern vertically separates the p-doped horizontal pattern from the n-doped pattern.
3 . The device of claim 1 , wherein the undoped pattern covers a top surface of the n-doped pattern.
4 . The device of claim 1 , wherein
the stack structure includes a plurality of structures that are horizontally spaced apart from each other, and
the device comprises a separation structure that separates the plurality of structures from each other and that extends into the n-doped pattern.
5 . The device of claim 4 , wherein the separation structure includes:
a metal contact electrically connected to the n-doped pattern; and
a separation dielectric pattern between the metal contact and the stack structure.
6 . The device of claim 1 , comprising a metal contact that extends through the p-doped pattern and the undoped pattern into the n-doped pattern.
7 . The device of claim 1 , wherein a doping concentration of the n-doped pattern increases continuously or discontinuously in a downward direction.
8 . The device of claim 1 , wherein a doping concentration of the p-doped horizontal pattern decreases continuously or discontinuously in a downward direction.
9 . The device of claim 1 , wherein
an upper portion of the p-doped vertical pattern is surrounded by the undoped pattern, and
a lower portion of the p-doped vertical pattern is surrounded by the n-doped pattern.
10 . The device of claim 9 , wherein, in a plan view, a doping concentration at the upper portion of the p-doped vertical pattern decreases continuously or discontinuously with decreasing distance from the undoped pattern.
11 . The device of claim 9 , wherein, in a plan view, a doping concentration at the lower portion of the p-doped vertical pattern decreases continuously or discontinuously with decreasing distance from the n-doped pattern.
12 . The device of claim 1 , comprising a p-contact plug electrically connected to the p-doped pattern,
wherein the p-doped pattern includes an ohmic region adjacent to the p-contact plug, and
wherein the ohmic region includes an n-type impurity.
13 . The device of claim 1 , wherein a width in a horizontal direction of the p-doped vertical pattern decreases in a downward direction.
14 . A three-dimensional semiconductor memory device comprising:
a circuit structure on a substrate;
a stack structure that includes a plurality of gate electrodes stacked on the circuit structure;
an n-doped pattern on the stack structure;
a vertical structure that extends through the stack structure into the n-doped pattern;
an undoped pattern on the n-doped pattern;
a p-doped pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure;
a metal contact electrically connected to the n-doped pattern; and
a p-contact plug electrically connected to the p-doped pattern.
15 . The device of claim 14 , wherein the p-doped pattern covers a top surface of the undoped pattern.
16 . The device of claim 14 , wherein the n-doped pattern includes:
a first n-doped region; and
a second n-doped region, wherein a doping concentration of the second n-doped region is less than a doping concentration of the first n-doped region, and
wherein the second n-doped region is closer than the first n-doped region to the undoped pattern.
17 . The device of claim 14 , wherein the p-doped pattern includes:
a first p-doped region; and
a second p-doped region, wherein a doping concentration of the second p-doped region is greater than a doping concentration of the first p-doped region, and
wherein the first p-doped region is closer than the second p-doped region to the undoped pattern.
18 . The device of claim 14 , wherein the metal contact extends into the n-doped pattern from a bottom or top end of the n-doped pattern.
19 . An electronic system comprising:
a three-dimensional semiconductor memory device; and
a controller electrically connected through an input/output pad to the three-dimensional semiconductor memory device, the controller configured to control the three-dimensional semiconductor memory device,
wherein the three-dimensional semiconductor memory device includes:
a circuit structure on a substrate;
a stack structure that includes a plurality of gate electrodes stacked on the circuit structure;
an n-doped pattern on the stack structure;
a vertical structure that extends through the stack structure into the n-doped pattern;
a p-doped pattern on the n-doped pattern; and
an undoped pattern between the n-doped pattern and then p-doped pattern,
wherein the p-doped pattern includes:
a p-doped horizontal pattern on the undoped pattern; and
a p-doped vertical pattern that extends through the undoped pattern and the n-doped pattern and that contacts with the vertical structure.
20 . The electronic system of claim 19 , wherein the undoped pattern vertically separates the p-doped horizontal pattern from the n-doped pattern.