Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.
1 . A semiconductor device comprising:
a first substrate;
a stacked body including a plurality of electrode layers that are provided above the first substrate and are stacked in a first direction;
a plurality of bit lines provided between the first substrate and a lowermost electrode layer among the plurality of electrode layers in the first direction, and each extending to cross the first direction;
a plurality of columnar portions, each of which extends in the first direction in the plurality of electrode layers and includes a first semiconductor layer;
a second semiconductor layer provided to contact the first semiconductor layer in each of the plurality of columnar portions; and
a conductive layer provided above an uppermost electrode layer among the plurality of electrode layers, extending to cross the first direction, and annularly surrounding the second semiconductor layer,
wherein the second semiconductor layer includes an impurity diffusion layer that has an impurity concentration higher than an impurity concentration of the first semiconductor layer.
2 . The device of claim 1 , comprising, as the first semiconductor layer, a plurality of first semiconductor layers provided in an array in an in-plane direction of the plurality of electrode layers,
wherein the second semiconductor layer is electrically connected to each of the plurality of first semiconductor layers.
3 . The device of claim 1 , wherein
the first substrate is provided in a first chip that includes a logic circuit; and
the plurality of electrode layers are provided in a second chip that is provided on the first chip and includes a memory cell array.
4 . The device of claim 1 , wherein the conductive layer is a polysilicon layer or a metal layer.
5 . The device of claim 1 , wherein the second semiconductor layer annularly surrounds the first semiconductor layer.
6 . The device of claim 1 , wherein
the first semiconductor layer has a columnar shape extending in the first direction; and
the second semiconductor layer has a columnar shape extending in the first direction on the first semiconductor layer.
7 . The device of claim 1 , wherein
the first semiconductor layer includes a first portion provided around a side face of a first insulator, and a second portion provided on the first insulator and the first portion; and
the second semiconductor layer is provided on the second portion.
8 . The device of claim 7 , further comprising a second insulator provided around a side face of the second portion to form an annular shape.
9 . The device of claim 7 , wherein the second semiconductor layer includes:
a first region provided above a plurality of first semiconductor layers; and
a plurality of second regions projecting from the first region toward upper portions of individual ones of the first semiconductor layers.
10 . The device of claim 1 , further comprising a source layer provided above the plurality of bit lines in the first direction, and electrically connected to the second semiconductor layer.