Semiconductor memory device and method of manufacturing semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a first bit line; a capacitor; and a first memory cell transistor and a second memory cell transistor that are coupled in series between the first bit line and the capacitor.
1 . A semiconductor memory device comprising:
a first bit line;
a first capacitor;
a first memory cell transistor and a second memory cell transistor that are coupled in series between the first bit line and the first capacitor;
a second bit line;
a second capacitor;
a third memory cell transistor and a fourth memory cell transistor that are coupled in series between the second bit line and the second capacitor;
a fifth memory cell transistor electrically coupled in series to the second memory cell transistor; and
a sixth memory cell transistor electrically coupled in series to the fourth memory cell transistor,
wherein
the first capacitor includes a first end configured to be electrically coupled to the first bit line, and a second end that is grounded,
the second capacitor includes a third end configured to be electrically coupled to the second bit line, and a fourth end that is grounded,
the first end and the third end are electrically separated,
the first end of the first capacitor is physically connected in series only to the fifth transistor and is not physically connected to any transistor other than the fifth transistor, and
the third end of the second capacitor is physically connected in series only to the sixth transistor and is not physically connected to any transistor other than the sixth transistor.
2 . The semiconductor memory device according to claim 1 , further comprising a select transistor electrically coupled to the first bit line,
the first memory cell transistor and the second memory cell transistor being coupled in series between the select transistor and the capacitor.
3 . A semiconductor memory device comprising:
a first bit line;
a first capacitor;
a first memory cell transistor and a second memory cell transistor that are coupled in series between the first bit line and the first capacitor;
a second bit line;
a second capacitor; and
a third memory cell transistor and a fourth memory cell transistor that are coupled in series between the second bit line and the second capacitor,
wherein
the first capacitor includes a first end configured to be electrically coupled to the first bit line, and a second end that is grounded,
the second capacitor includes a third end configured to be electrically coupled to the second bit line, and a fourth end that is grounded, and
the first end and the third end are electrically separated,
the first end of the first capacitor is physically connected only to one transistor of all transistors, including the first transistor and the second transistor, connecting between the first bit line and the first capacitor, and
the third end of the second capacitor is physically connected only to one transistor of all transistors, including the third transistor and the fourth transistor, connecting between the second bit line and the second capacitor.
4 . The semiconductor memory device according to claim 3 , further comprising a select transistor electrically coupled to the first bit line,
the first memory cell transistor and the second memory cell transistor being coupled in series between the select transistor and the capacitor.