IP Library Granted Patent US 12713614
Granted Patent B2
US 12713614 · App. 18/179,865 · Granted Aug 18, 2026

Semiconductor device and method for manufacturing semiconductor device

Inventors: Minoru Oda (Yokkaichi Mie, JP); Taichi Iwasaki (Yokkaichi Mie, JP)
Assignee: Kioxia Corporation
H10B43/35H10B41/27H10B41/35H10B43/27
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Quick Facts
Patent No.
US 12713614
App. No.
18/179,865
Granted
Aug 18, 2026
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface. The semiconductor substrate has therein a first region. The first region is at the first surface and contains a dopant of a first conductivity type. A first contact contacts the first region at the first surface. The first contact has a first metal layer that contacts the first region, a second metal layer covering the first metal layer, and a third metal layer covering the second metal layer.

Claims (72)

1 . A semiconductor device, comprising:

a semiconductor substrate having a first surface;

a first region in the semiconductor substrate, the first region being at the first surface and containing a dopant of a first conductivity type; and

a first contact contacting the first region at the first surface, the first contact comprising:

a first metal layer that contacts the first region,

a second metal layer covering the first metal layer,

a third metal layer covering the second metal layer, and

a fourth metal layer on the third metal layer, wherein

the second metal layer is between the first and fourth metal layer in a direction orthogonal to the first surface.

2 . The semiconductor device according to claim 1 , further comprising:

an insulating material surrounding the first contact in a plane parallel to the first surface, wherein

the first metal layer, second metal layer, and third metal layer are on a sidewall of the first contact with the first metal layer contacting the insulating material, and

the second metal layer is between the first and fourth metal layer in a direction parallel to the first surface.

3 . The semiconductor device according to claim 2 , wherein the fourth metal layer fills an interior of the first contact adjacent to the sidewall.

4 . The semiconductor device according to claim 3 , wherein

the first metal layer is titanium nitride,

the second metal layer is a metallic film of titanium, hafnium, or aluminum,

the third metal layer is titanium nitride, and

the fourth metal layer is tungsten metal.

5 . The semiconductor device according to claim 1 , further comprising:

a second region in the semiconductor substrate at the first surface, the second region being spaced from the first region and containing a dopant of the first conductivity type; and

an electrode on the first surface at a position between the first region and the second region.

6 . The semiconductor device according to claim 5 , further comprising:

a second contact contacting the second region at the first surface, the second contact comprising:

a fifth metal layer that contacts the second region,

a sixth metal layer covering the fifth metal layer, and

a seventh metal covering the sixth metal layer.

7 . The semiconductor device according to claim 6 , wherein the sixth metal layer comprises at least one metal selected from titanium, hafnium, and aluminum.

8 . The semiconductor device according to claim 7 , wherein the fifth metal layer and the seventh metal layer each comprise titanium nitride.

9 . The semiconductor device according to claim 1 , wherein the second metal layer comprises at least one metal selected from titanium, hafnium, and aluminum.

10 . The semiconductor device according to claim 9 , wherein the first metal layer and the third metal layer each comprise titanium nitride.

11 . The semiconductor device according to claim 1 , further comprising:

a memory cell array region, wherein

the first contact is between the memory cell array region and the semiconductor substrate.

12 . A semiconductor device, comprising:

a semiconductor substrate having a first surface;

a first region in semiconductor substrate at the first surface and containing dopant of a first conductivity type;

an interlayer insulating film above the first surface in a first direction; and

a contact extending through the interlayer insulating film in the first direction and electrically contacting the first region, wherein

a bottom of the contact adjacent to the first surface in the first direction and a sidewall of the contact adjacent to the interlayer insulating film in a second direction parallel to the first surface have a stacked layer structure comprising:

a first barrier metal layer that contacts the first region and the interlayer insulating film,

a first metallic layer covering the first metal layer, and

a second barrier metal layer covering the first metallic layer, and

an interior of the contact is filled with a second metallic layer.

13 . The semiconductor device according to claim 12 , wherein the first metallic layer comprises at least one metal selected from titanium, hafnium, and aluminum.

14 . The semiconductor device according to claim 13 , wherein the first barrier metal layer and the second barrier metal layer each comprise titanium nitride.

15 . The semiconductor device according to claim 14 , wherein the second metallic layer is tungsten.

16 . The semiconductor device according to claim 12 , wherein the first metallic layer is hafnium.

17 . A semiconductor device, comprising:

a semiconductor substrate having a first surface;

a first region in the semiconductor substrate, the first region being at the first surface and containing a dopant of a first conductivity type; and

a first contact contacting the first region at the first surface, the first contact comprising:

a first metal layer that contacts the first region,

a second metal layer covering the first metal layer,

a third metal layer covering the second metal layer, wherein

the second metal layer comprises at least one metal selected from titanium, hafnium, and aluminum, and

the first metal layer and the third metal layer each comprise titanium nitride.

18 . The semiconductor device according to claim 17 , further comprising:

a memory cell array region, wherein

the first contact is between the memory cell array region and the semiconductor substrate.

19 . The semiconductor device according to claim 18 , further comprising:

a second region in semiconductor substrate at the first surface, the second region being spaced from the first region and containing a dopant of the first conductivity type;

an electrode on the first surface at a position between the first region and the second region; and

a second contact contacting the second region at the first surface, the second contact comprising:

a fourth metal layer that contacts the second region,

a fifth metal layer covering the fourth metal layer, and

a sixth metal covering the fifth metal layer, wherein

the fifth metal layer comprises at least one metal selected from titanium, hafnium, and aluminum, and

the fourth metal layer and the sixth metal layer each comprise titanium nitride.

20 . The semiconductor device according to claim 17 , wherein the first contact further comprises:

a fourth metal layer on the third metal layer, wherein

the fourth metal layer is tungsten metal.