Memory device
A memory device and a method of manufacturing the same are provided. The memory device includes a substrate, a memory cell array, and a memory cell interconnection structure. The memory cell array is disposed on the substrate and includes a plurality of memory cells. Each of the plurality of memory cells includes a transistor unit and a memory unit that are electrically connected to each other. The memory cell interconnection structure is disposed on the substrate, and is configured to establish an electrical connection between the plurality of memory cells. A plurality of source lines are embedded in a dielectric layer that directly covers the substrate. Each of the plurality of source lines is disposed on the substrate, and comes in direct contact with a source region of a corresponding one of the transistor units.
1 . A memory device, comprising:
a substrate;
a memory cell array disposed on the substrate and including a plurality of memory cells, wherein each of the plurality of memory cells includes:
a transistor unit, wherein the transistor unit includes a source region, a drain region, and a gate structure; and
a memory unit electrically connected to the transistor unit; and
a memory cell interconnection structure disposed on the substrate, wherein the memory cell interconnection structure is configured to establish an electrical connection between the plurality of memory cells, and the memory cell interconnection structure includes:
a dielectric layer directly covering the substrate and the transistor units; and
a plurality of source lines disposed on the substrate and extending along a first direction, wherein each of the plurality of source lines is embedded in the dielectric layer and comes in contact with the source region of a corresponding one of the transistor units;
wherein the substrate further includes a plurality of isolation structures formed in the substrate, and each of the plurality of isolation structures extends along the second direction and intersects with the plurality of source lines, so as to separate any two of the transistor units that are arranged along the first direction and adjacent to each other; wherein each of the plurality of isolation structures has a plurality of insulation portions that respectively overlap with the plurality of source lines, a surface of each of the plurality of insulation portions has a recess, a part of each of the plurality of source lines is filled into the recess of a corresponding one of the plurality of insulation portions and directly contacts the corresponding insulation portion, and a depth of each of the recesses is greater than a depth of the source region in the substrate.
2 . The memory device according to claim 1 , wherein the memory cell interconnection structure further includes:
a plurality of bit lines extending along a second direction, wherein each of the plurality of bit lines is connected to an upper electrode of a corresponding one of the memory units; and
a plurality of drain conductive structures, wherein each of the plurality of drain conductive structures is connected to a lower electrode of a corresponding one of the memory units and the drain region of a corresponding one of the transistor units.
3 . The memory device according to claim 1 , wherein the transistor units of the plurality of memory cells are arranged in a plurality of rows along the first direction, and the gate structures of the transistor units in a same row are connected to each other, so as to form a common gate line that extends along the first direction.
4 . The memory device according to claim 1 , wherein the gate structure of the transistor unit is disposed on the substate, and includes a first gate stack portion and a second gate stack portion; wherein the first gate stack portion and the second gate stack portion are spaced apart from each other and are respectively disposed on opposite sides of the drain region; wherein the first gate stack portion is electrically connected to the second gate stack portion.
5 . The memory device according to claim 1 , wherein a top surface of each of the plurality of source lines is higher than a top end of the gate structure, and a material of each of the plurality of source lines is selected from a group consisting of metal, alloy, conductive oxide, conductive nitride, and any combination thereof.
6 . The memory device according to claim 1 , wherein the memory unit is a resistive random-access memory, a conductive bridging random access memory, a magnetoresistive random access memory, a phase change random access memory, or a ferroelectrical random access memory.