Wafer level packaging process for thin film inductors
An integrated circuit (IC) package, including an integrated circuit (IC) die including an input/output (I/O) pad, and a vertical thin-film inductor (TFI) extending vertically substantially from the I/O pad to a solder bump.
1 . An integrated circuit (IC) package, comprising:
an integrated circuit (IC) die including an input/output (I/O) pad; and
a vertical thin-film inductor (TFI) extending vertically substantially from the I/O pad to a solder bump,
wherein the vertical TFI comprises an electrical conducting pillar extending vertically substantially from the I/O pad to a solder bump, and
wherein the vertical TFI further comprises a first magnetic semi-ring layer electrically isolated from the electrical conducting pillar, wherein the electrical conducting pillar extends coaxially through the first magnetic semi-ring layer.
2 . The IC package of claim 1 , wherein the electrical conducting pillar comprises copper.
3 . The IC package of claim 1 , wherein the first magnetic semi-ring layer comprises cobalt, zirconium, tantalum (CTZ), cobalt, zirconium, tantalum, boron (CZTB), CZT+tantalum (Ta), CZT+CZT oxide, or nickel-iron (NiFe)+Ta.
4 . The IC package of claim 1 , wherein the first magnetic semi-ring layer comprises a stack of alternating material layers.
5 . The IC package of claim 4 , wherein the stack of alternating material layers comprises CZTB and Ta, CZT and CZT oxide, or NiFE and Ta.
6 . The IC package of claim 1 , wherein the first magnetic semi-ring layer includes a first angular gap.
7 . The IC package of claim 1 , wherein the vertical TFI further comprises a second magnetic semi-ring layer electrically isolated from the first magnetic semi-ring layer and the electrical conducting pillar, wherein the electrical conducting pillar extends coaxially through the second magnetic semi-ring layer.
8 . The IC package of claim 7 , wherein the second magnetic semi-ring layer comprises CTZ, CZTB, CZT+Ta, CZT+CZT oxide, or NiFe+Ta.
9 . The IC package of claim 7 , wherein the second magnetic semi-ring layer comprises a stack of alternating material layers.
10 . The IC package of claim 9 , wherein the stack of alternating material layers comprises CZTB and Ta, CZT and CZT oxide, or NiFE and Ta.
11 . The IC package of claim 7 , wherein:
the first magnetic semi-ring layer includes a first angular gap; and
the second magnetic semi-ring layer includes a second angular gap.
12 . The IC package of claim 11 , wherein the first and second angular gaps are substantially vertically aligned.
13 . The IC package of claim 7 , wherein the vertical TFI further comprises an electrical insulating layer electrically isolating the first magnetic semi-ring layer from the second magnetic semi-ring layer.
14 . The IC package of claim 13 , wherein the electrical insulating layer comprises silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or a polymer.
15 . The IC package of claim 7 , wherein the vertical TFI further comprises an electrical insulating layer electrically isolating the first and second magnetic semi-ring layers from the electrical conducting pillar.
16 . The IC package of claim 15 , wherein the electrical insulating layer comprises silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or a polymer.
17 . The IC package of claim 1 , further comprising a passivation layer coaxially surrounding the electrical conducting pillar.
18 . The IC package of claim 17 , wherein the passivation layer comprises a polymer or an epoxy mold compound.
19 . The IC package of claim 18 , wherein the polymer comprises polyimide or polybenzoxazoles (PBO).
20 . A method of fabricating an integrated circuit (IC) package, comprising:
providing an integrated circuit (IC) including an input/output (I/O) pad;
forming a vertical thin-film inductor (TFI) extending vertically from substantially the I/O pad, wherein forming the vertical TFI comprises forming an electrical conducting pillar extending vertically from substantially the I/O pad to the solder bump;
forming a solder bump over the vertical TFI; and
forming a first magnetic semi-ring layer coaxially surrounding and electrically isolated from the electrical conducting pillar.
21 . The method of claim 20 , wherein the first magnetic semi-ring layer includes a first angular gap.
22 . The method of claim 20 , further comprising forming a second magnetic semi-ring layer coaxially surrounding and electrically isolated from the electrical conducting pillar, wherein the second magnetic semi-ring layer is substantially vertically aligned above and electrically isolated from the first magnetic semi-ring layer.
23 . The method of claim 22 , wherein at least one of the first or second magnetic semi-ring layer each comprises cobalt, zirconium, tantalum (CTZ), cobalt, zirconium, tantalum, boron (CZTB), CZT+tantalum (Ta), CZT+CZT oxide, or nickel-iron (NiFe)+Ta.
24 . The method of claim 22 , wherein at least one of the first or second magnetic semi-ring layer comprises a stack of alternating material layers including CZTB and Ta, CZT and CZT oxide, or NiFE and Ta.
25 . The method of claim 22 , wherein:
the first magnetic semi-ring layer includes a first angular gap; and
the second magnetic semi-ring layer includes a second angular gap.
26 . The method of claim 25 , wherein the first and second angular gaps are substantially vertically aligned.