Three-dimensional integrated circuit resistors
Compact polysilicon resistor structures, particularly for RF ICs, and methods of fabricating such structures. Embodiments include three-dimensional (3-D) IC structures that include a 3-D resistor configuration comprising disjointed polysilicon segments spaced by at least one IC substrate and connected by one or more conductive through-substrate vias (TSVs). Compared to the prior art, embodiments of the present invention provide a reduction in IC area required for a polysilicon resistor and result in the same performance while maintaining low parasitic capacitance. For example, by taking advantage of the substrate cross-sectional height, embodiments of the invention can achieve the same resistive performance while reducing area allocation by more than 30%.
1 . A three-dimensional integrated circuit structure including at least two disjointed polysilicon resistor segments spaced by a pair of bonded integrated circuit substrates and electrically connected by at least one through-substrate via.
2 . The three-dimensional integrated circuit structure of claim 1 , further including a first electrical contact electrically coupled to a first end polysilicon segment of the at least two disjointed polysilicon resistor segments, and a second electrical contact electrically coupled to a second end polysilicon segment of the at least two disjointed polysilicon resistor segments.
3 . The three-dimensional integrated circuit structure of claim 2 , further including:
(a) a first electrical contact electrically coupled to a first end polysilicon segment of the at least two disjointed polysilicon resistor segments;
(b) a second electrical contact electrically coupled to a second end polysilicon segment of the at least two disjointed polysilicon resistor segments; and
(c) at least one additional electrical contact electrically coupled to an associated segment of the at least two disjointed polysilicon resistor segments at a connection point located along a current path between the first electrical contact and the second electrical contact.
4 . The three-dimensional integrated circuit structure of claim 1 , wherein most of the at least two disjointed polysilicon resistor segments are substantially “L” shaped.
5 . The three-dimensional integrated circuit structure of claim 1 , wherein a first set of the at least two disjointed polysilicon resistor segments are substantially “Z” shaped and a second set of the at least two disjointed polysilicon resistor segments are substantially “I” shaped.
6 . The three-dimensional integrated circuit structure of claim 1 , wherein a first set of the at least two disjointed polysilicon resistor segments are substantially “Z” shaped and a second set of the at least two disjointed polysilicon resistor segments are substantially “C” shaped.
7 . The three-dimensional integrated circuit structure of claim 6 , wherein the “C” shaped polysilicon segments at least partially underlap associated ones of the “Z” shaped polysilicon segments.
8 . The three-dimensional integrated circuit structure of claim 1 , wherein the pair of bonded integrated circuit substrates comprises a first substrate formed of a first material and a second substrate formed of a second material different from the first material.
9 . The three-dimensional integrated circuit structure of claim 1 , wherein each of the pair of bonded integrated circuit substrates has a front-side including a substructure and a backside, and wherein the pair of bonded integrated circuit substrates are bonded at their respective backsides such that the disjointed polysilicon resistor segments are disposed on opposing outward-facing front-sides of the three-dimensional integrated circuit structure.
10 . The three-dimensional integrated circuit structure of claim 1 , wherein the at least one through-substrate via comprises a first via segment extending through the first substrate and a second via segment extending through the second substrate, and wherein the first and second via segments are aligned and electrically coupled at a bonding interface between the pair of bonded integrated circuit substrates.
11 . The three-dimensional integrated circuit structure of claim 1 , wherein at least one of the pair of bonded integrated circuit substrates comprises a trap-rich silicon layer or a high-resistivity silicon substrate.
12 . A three-dimensional integrated circuit structure comprising:
a pair of integrated circuit substrates comprising a first integrated circuit substrate and a second integrated circuit substrate, each of the integrated circuit substrates having a front-side including a substructure and a backside, the pair of integrated circuit substrates being bonded at their respective backsides;
wherein
a plurality of disjointed polysilicon resistor segments comprising a first polysilicon resistor segment disposed on a front-side of the first integrated circuit substrate and a second polysilicon resistor segment disposed on a front-side of the second integrated circuit substrate, and
at least one through-substrate via electrically connected between the first polysilicon resistor segment and the second polysilicon resistor segment.
13 . The three-dimensional integrated circuit structure of claim 12 , wherein the first polysilicon resistor segment and the second polysilicon resistor segment are spaced apart by the pair of bonded integrated circuit substrates.
14 . The three-dimensional integrated circuit structure of claim 12 , wherein the at least one through-substrate via comprises a first via segment extending through the first integrated circuit substrate and a second via segment extending through the second integrated circuit substrate, and wherein the first and second via segments are aligned and electrically coupled at a bonding interface between the pair of integrated circuit substrates.