IP Library Granted Patent US 12713632
Granted Patent B2
US 12713632 · App. 18/638,923 · Granted Aug 18, 2026

Semiconductor device

Inventors: Jinseong Heo (Seoul, KR); Taehwan Moon (Suwon-si, KR); Hagyoul Bae (Hanam-si, KR); Seunggeol Nam (Suwon-si, KR); Sangwook Kim (Seongnam-si, KR); Kwanghee Lee (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10D1/682H10B63/00H10B69/00H10D1/40H10K10/50H10K19/201
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Quick Facts
Patent No.
US 12713632
App. No.
18/638,923
Granted
Aug 18, 2026
Kind
B2
Abstract

A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

Claims (55)

1 . A semiconductor device, comprising:

a first electrode;

a second electrode isolated from direct contact with the first electrode;

a ferroelectric layer;

a conductive metal oxide layer; and

a semiconductor layer,

wherein the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer are between the first electrode and the second electrode,

wherein the conductive metal oxide layer is directly between the ferroelectric layer and the semiconductor layer such that the conductive metal oxide layer includes a metal oxide material that is in direct contact with both the ferroelectric layer and the semiconductor layer,

wherein the second electrode includes at least one of a metal nitride or a metal oxide, and the semiconductor layer is in direct contact with the at least one of the metal nitride or the metal oxide of the second electrode, and

wherein the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer each independently have a thickness between about 0.1 nm and about 20 nm.

2 . A semiconductor device, comprising:

a first electrode;

a second electrode isolated from direct contact with the first electrode;

a ferroelectric layer;

a conductive metal oxide layer; and

a semiconductor layer,

wherein the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer are between the first electrode and the second electrode,

wherein the conductive metal oxide layer is directly between the ferroelectric layer and the semiconductor layer such that the conductive metal oxide layer includes a metal oxide material that is in direct contact with both the ferroelectric layer and the semiconductor layer,

wherein the semiconductor layer is in direct contact with the second electrode, the second electrode including at least one of a metal nitride or a metal oxide, and

wherein the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer include a same kind of metal oxide.

3 . The semiconductor device of claim 1 , wherein

the semiconductor device is configured to control a polarization direction of a polarization of the ferroelectric layer according to a direction of an electric field formed between the first electrode and the second electrode, and

the semiconductor device is further configured to form a depletion region or an accumulation region in the semiconductor layer according to the polarization direction of the polarization of the ferroelectric layer.

4 . The semiconductor device of claim 1 , wherein the conductive metal oxide layer includes one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

5 . The semiconductor device of claim 1 , wherein the conductive metal oxide layer has an electrical conductivity equal to or greater than about 100 S/cm.

6 . The semiconductor device of claim 1 , wherein the semiconductor layer has an energy bandgap equal to or less than about 5.0 eV.

7 . The semiconductor device of claim 1 , wherein the ferroelectric layer includes, as a base material, a material represented by MO 2 , where M is Hf, Zr, or a combination thereof.

8 . The semiconductor device of claim 1 , wherein

the ferroelectric layer includes, as a base material, a material represented by MO 2 , where M is Hf, Zr, or a combination thereof, and

the ferroelectric layer further includes a dopant material including one or more materials selected from the group consisting of C, Ge, Sn, Y, La, Gd, Mg, Ca, Sr, and any combination thereof.

9 . The semiconductor device of claim 1 , wherein the ferroelectric layer includes an orthorhombic crystal phase.

10 . The semiconductor device of claim 1 , wherein the ferroelectric layer has a crystal structure having a (111) crystal direction, a (001) crystal direction, or a combination thereof.

11 . The semiconductor device of claim 1 , wherein the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer each include a respective metal oxide.

12 . The semiconductor device of claim 1 , wherein the semiconductor device is configured to have a variable resistance between a high resistance value and a low resistance value that is generated according to a polarization direction of a polarization of the ferroelectric layer, the semiconductor device having a resistance ratio that is a ratio of the high resistance value and the low resistance value, the resistance ratio being 5.0 or more.

13 . The semiconductor device of claim 1 , wherein the first electrode and the second electrode each independently include at least one metal nitride, at least one metal oxide, or any combination thereof.

14 . The semiconductor device of claim 1 , further comprising:

a memory element that is configured to store information.

15 . A semiconductor apparatus, comprising:

a plurality of first electrode lines on a substrate, the plurality of first electrode lines extending in parallel to an upper surface of the substrate, the plurality of first electrode lines extending in a first direction;

a plurality of second electrode lines on the plurality of first electrode lines, the plurality of second electrode lines extending in parallel to the upper surface of the substrate, the plurality of second electrode lines extending in a second direction that is different from the first direction; and

a first semiconductor device between the plurality of first electrode lines and the plurality of second electrode lines at an intersection of one first electrode line of the plurality of first electrode lines and one second electrode line of the plurality of second electrode lines where the one first electrode line and the one second electrode line overlap each other in a vertical direction that is perpendicular to the first direction and is perpendicular to the second direction, the first semiconductor device comprising the semiconductor device according to claim 1 .

16 . The semiconductor apparatus of claim 15 , further comprising:

a plurality of third electrode lines on the plurality of first electrode lines and the plurality of second electrode lines, the plurality of third electrode lines extending in the first direction; and

a second semiconductor device between the plurality of second electrode lines and the plurality of third electrode lines at an intersection of the one second electrode line and one third electrode line of the plurality of third electrode lines where the one second electrode line and the one third electrode line overlap each other in the vertical direction, the second semiconductor device having a same structure as the first semiconductor device.

17 . A semiconductor apparatus, comprising:

a stack structure in which a plurality of insulating layers and a plurality of first electrodes are alternately and repeatedly stacked in a vertical direction; and

a cell string including a ferroelectric layer, a conductive metal oxide layer, a semiconductor layer, and a second electrode,

wherein the cell string penetrates the stack structure in the vertical direction,

wherein, in the cell string, the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer are between a first electrode of the plurality of first electrodes and the second electrode,

wherein the conductive metal oxide layer is directly between the ferroelectric layer and the semiconductor layer such that the conductive metal oxide layer includes a metal oxide material that is in direct contact with both the ferroelectric layer and the semiconductor layer,

wherein the second electrode includes at least one of a metal nitride or a metal oxide, and the semiconductor layer is in direct contact with the at least one of the metal nitride or the metal oxide of the second electrode, and

wherein the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer each independently have a thickness between about 0.1 nm and about 20 nm.

18 . The semiconductor apparatus of claim 17 , wherein

the ferroelectric layer, the conductive metal oxide layer, the semiconductor layer, and the second electrode extend in the vertical direction through the stack structure, and

the second electrode is at a center portion of the cell string, and the ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer concentrically surround the second electrode.