Methods of forming semiconductor devices
In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.
1 . A method comprising:
growing a source/drain region adjacent a dummy gate, the dummy gate disposed on a channel region of a semiconductor fin, the semiconductor fin protruding above an isolation region;
removing the dummy gate to expose the channel region of the semiconductor fin;
after removing the dummy gate, trimming the channel region by performing a plurality of oxidation and etch cycles, each of the oxidation and etch cycles removing a same amount of the channel region; and
forming a metal gate on the channel region, the metal gate extending along a sidewall of the channel region and along a top surface of the isolation region.
2 . The method of claim 1 , wherein performing the plurality of oxidation and etch cycles comprises:
oxidizing the channel region by performing a thermal oxidation process;
etching the channel region by performing an oxide removal process; and
repeating the thermal oxidation process and the oxide removal process a quantity of times.
3 . The method of claim 2 , wherein the thermal oxidation process is performed at a temperature of from 300° C. to 1050° C. and for a time span of from 10 seconds to 600 seconds.
4 . The method of claim 2 , wherein the oxide removal process is performed with dilute hydrofluoric acid.
5 . The method of claim 1 , wherein trimming the channel region reduces a width of the channel region above the top surface of the isolation region.
6 . The method of claim 1 , wherein trimming the channel region reduces a height of the channel region above the top surface of the isolation region.
7 . A method comprising:
forming a gate spacer on a lightly doped source/drain region of a semiconductor fin, the gate spacer adjacent a dummy gate, the dummy gate disposed on a channel region of the semiconductor fin;
removing the dummy gate to expose the channel region of the semiconductor fin;
after removing the dummy gate, trimming the channel region of the semiconductor fin by performing a plurality of oxidation and etch cycles, the channel region of the semiconductor fin having a lesser width than the lightly doped source/drain region of the semiconductor fin after performing the oxidation and etch cycles; and
forming a metal gate on the channel region of the semiconductor fin.
8 . The method of claim 7 , wherein each of the oxidation and etch cycles removes a same amount of the channel region of the semiconductor fin.
9 . The method of claim 7 , wherein the channel region of the semiconductor fin has a lesser height than the lightly doped source/drain region of the semiconductor fin after performing the oxidation and etch cycles.
10 . The method of claim 7 , wherein after performing the oxidation and etch cycles, the channel region of the semiconductor fin and the lightly doped source/drain region of the semiconductor fin have a step interface.
11 . The method of claim 7 , wherein after performing the oxidation and etch cycles, the channel region of the semiconductor fin and the lightly doped source/drain region of the semiconductor fin have a linear interface.
12 . The method of claim 7 , wherein after performing the oxidation and etch cycles, the channel region of the semiconductor fin and the lightly doped source/drain region of the semiconductor fin have a curved interface.
13 . The method of claim 7 , further comprising:
growing an epitaxial source/drain region in the lightly doped source/drain region of the semiconductor fin.
14 . A method comprising:
forming a dummy gate on a channel region;
growing an epitaxial source/drain adjacent the channel region;
removing the dummy gate to expose the channel region;
after removing the dummy gate, trimming the channel region by performing a plurality of oxidation and etch cycles, the channel region having a first width before the trimming, the channel region having a second width after the trimming, the second width being less than the first width; and
forming a metal gate on the channel region.
15 . The method of claim 14 , wherein the channel region has a first height before the trimming, the channel region has a second height after the trimming, and the second height is less than the first height.
16 . The method of claim 14 , wherein performing the plurality of oxidation and etch cycles comprises:
oxidizing the channel region by performing an oxidation process;
etching the channel region by performing an oxide removal process; and
repeating the oxidation process and the oxide removal process a quantity of times.
17 . The method of claim 16 , wherein a same amount of the channel region is removed each time the oxidation process and the oxide removal process are repeated.
18 . The method of claim 16 , wherein the oxidation process is a thermal oxidation process.
19 . The method of claim 16 , wherein the oxidation process is a chemical oxidation process.
20 . The method of claim 16 , wherein the oxide removal process is a chemical oxide removal process.