Method for manufacturing a power transistor and power transistor

1 . A method for manufacturing a power transistor, comprising the steps:

applying a first epitaxial layer including a first doping concentration to a front side of a semiconductor substrate;

producing an expansion layer, which is situated inside the first epitaxial layer,

producing various implanted areas starting from the front side of the semiconductor substrate;

producing a trench structure and field shielding regions starting from the front side of the semiconductor substrate and into the first epitaxial layer;

producing first isolation areas in surroundings of the trench structure;

producing transistor heads; and

applying metal layers,

wherein each of the field shielding regions are situated laterally spaced apart from the trench structure, and the trench structure has a lesser depth than the field shielding regions,

wherein an entirety of the expansion region is situated below the depth of the trench structure,

wherein the first isolation areas have an increased thickness in an area of trench ends and below gate contacts,

wherein the expansion layer has a thickness of 0.5 μm to 3 μm, and is doped with a concentration between 1×10 15 atoms/cm 3 and 1×10 18 atoms/cm 3 , and wherein the expansion layer overlaps with the field shielding regions.

2 . The method as recited in claim 1 , wherein the expansion layer is produced during the application of the first epitaxial layer for a certain duration by increasing the first doping concentration.

3 . The method as recited in claim 1 , wherein the expansion layer is produced using implantation of dopants.

4 . The method as recited in claim 1 , wherein the trench structure is produced with using a hard mask made of silicon dioxide, in that the hard mask is elevated after a structuring and is reduced using dry etching.

5 . The method as recited in claim 1 , wherein the first isolation areas in an area of trench openings and below the gate contacts are enlarged using a structured mask.

6 . The method as recited in claim 1 , wherein prior to the application of the first epitaxial layer, a second epitaxial layer is applied to the front side of the semiconductor substrate, so that the second epitaxial layer is situated between the front side of the semiconductor substrate and the first epitaxial layer, the second epitaxial layer including a dopant profile which decreases starting from a transition of the front side of the semiconductor substrate to the second epitaxial layer to a transition of the second epitaxial layer to the first epitaxial layer.

7 . The method as recited in claim 1 , further comprising:

producing channel regions at a front side of the first epitaxial layer; and

producing source regions situated on the channel regions;

wherein the first isolation areas are elevated at certain points in surroundings of the trench;

wherein:

the expansion layer forms an expansion region of the power transistor, the expansion region being situated at a rear side of the trench; and

the trench has a trench width of between 300 nm and 1200 nm.

8 . The method as recited in claim 7 , wherein the trench width is less than 850 nm.

9 . The method as recited in claim 7 , wherein the semiconductor substrate includes silicon carbide or gallium nitride.