FinFET isolation structure
A device includes a semiconductive substrate, a stop layer, a semiconductive fin, a fin isolation structure, and a source/drain epitaxial layer. The stop layer is over the semiconductive substrate and includes SiGeO x , SiGe, SiP or SiPO x , where x is greater than 0. The semiconductive fin is over the stop layer. The fin isolation structure is connected to a sidewall of the semiconductive fin. The source/drain epitaxial layer is adjacent to the semiconductive fin. The semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure.
1 . A device, comprising:
a semiconductive substrate;
a stop layer over the semiconductive substrate and comprising SiGeO x , SiGe, SiP or SiPO x , where x is greater than 0;
a semiconductive fin over the stop layer;
a fin isolation structure connected to a sidewall of the semiconductive fin; and
a source/drain epitaxial layer adjacent to the semiconductive fin, wherein the semiconductive fin is between the source/drain epitaxial layer and the fin isolation structure, and the source/drain epitaxial layer is separated from the semiconductive substrate by the stop layer.
2 . The device of claim 1 , wherein a top surface of the fin isolation structure is higher than a top surface of the semiconductive fin.
3 . The device of claim 1 , wherein the semiconductive fin is separated from the semiconductive substrate by the stop layer.
4 . The device of claim 1 , wherein a bottom surface of the semiconductive fin is substantially coplanar with a bottom surface of the source/drain epitaxial layer.
5 . The device of claim 1 , wherein the fin isolation structure is in contact with a sidewall of the stop layer.
6 . The device of claim 1 , wherein the fin isolation structure is in contact with the semiconductive substrate.
7 . A device, comprising:
a semiconductive substrate;
a semiconductive fin over the semiconductive substrate;
a stop layer between the semiconductive fin and the semiconductive substrate;
a source/drain epitaxial layer connected to the semiconductive fin; and
a fin isolation structure over the semiconductive substrate and comprising:
a top portion having a first linear sidewall; and
a bottom portion having a second linear sidewall inclined to the first linear sidewall of the top portion, wherein an interface between the top portion and the bottom portion of the fin isolation structure is lower than a top surface of the source/drain epitaxial layer.
8 . The device of claim 1 , wherein a portion of the fin isolation structure is embedded in the semiconductive substrate.
9 . The device of claim 7 , wherein the interface between the top portion and the bottom portion of the fin isolation structure is lower than a top surface of the semiconductive fin.
10 . The device of claim 7 , wherein a bottom surface of the fin isolation structure is higher than a top surface of the semiconductive substrate.
11 . The device of claim 7 , wherein the second linear sidewall of the bottom portion of the fin isolation structure and a top surface of the stop layer form an acute angle in a cross-sectional view.
12 . The device of claim 7 , wherein the semiconductive fin has a bottom portion tapering towards the stop layer.
13 . The device of claim 7 , wherein a bottom surface of the bottom portion of the fin isolation structure is substantially flat.
14 . The device of claim 7 , wherein a bottom surface of the bottom portion of the fin isolation structure is substantially coplanar with a bottom surface of the source/drain epitaxial layer.
15 . A device, comprising:
a semiconductive substrate;
a fin isolation structure over the semiconductive substrate;
a stop layer over the semiconductive substrate and in contact with a sidewall of the fin isolation structure;
a semiconductive fin over the stop layer and in contact with the sidewall of the fin isolation structure; and
a gate spacer over the semiconductive fin and in contact with the sidewall of the fin isolation structure.
16 . The device of claim 15 , further comprising a gate dielectric layer between the semiconductive fin and the gate spacer, wherein the gate dielectric layer is in contact with the sidewall of the fin isolation structure.
17 . The device of claim 15 , further comprising a source/drain epitaxial layer over the stop layer and separated from the fin isolation structure by the semiconductive fin.
18 . The device of claim 15 , wherein a bottom surface of the fin isolation structure is convex.
19 . The device of claim 15 , wherein a bottom surface of the fin isolation structure is substantially flat.
20 . The device of claim 15 , wherein the semiconductive substrate is in contact with the sidewall of the fin isolation structure.