Semiconductor memory device
A semiconductor memory device includes bit lines disposed on a substrate and extending in a first direction in parallel to each other, a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines, a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer, a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern, a first channel pattern located on the source pattern, a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines, and a landing pad on the first channel pattern.
1 . A semiconductor memory device comprising:
bit lines disposed on a substrate and extending in a first direction in parallel to each other;
a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines;
a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer;
a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern,
a first channel pattern located on the source pattern,
a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines; and
a landing pad on the first channel pattern,
wherein a portion of the source pattern extends between a first side surface of a corresponding one of the bit lines and the hydrogen supply insulating layer and is in contact with the first side surface.
2 . The semiconductor memory device of claim 1 , wherein a concentration of hydrogen in the hydrogen supply insulating layer ranges from 0.1 at % to 5 at %.
3 . The semiconductor memory device of claim 1 , wherein the hydrogen diffusion barrier layer has a single-layered or multi-layered structure of at least one of silicon nitride and aluminum oxide.
4 . The semiconductor memory device of claim 1 , wherein the corresponding one of the bit lines has a second side surface opposite to the first side surface, and
wherein another portion of the source pattern extends between the second side surface of the corresponding one of the bit lines and the hydrogen supply insulating layer and is in contact with the second side surface.
5 . The semiconductor memory device of claim 1 , wherein a top surface of the first word line is located at a first level,
wherein the landing pad includes a protruding portion which extends toward the first channel pattern in a vertical direction and has the same width as the first channel pattern in the first direction, and
wherein a bottom surface of the protruding portion is located at a second level lower than the first level.
6 . The semiconductor memory device of claim 1 , wherein the first channel pattern penetrates the hydrogen diffusion barrier layer so as to be in contact with the source pattern.
7 . The semiconductor memory device of claim 1 , further comprising:
a second channel pattern which is located on the source pattern and is adjacent to the first channel pattern; and
a second word line which is located between the first word line and the second channel pattern and is closer to the second channel pattern than the first word line in the first direction.
8 . The semiconductor memory device of claim 7 , further comprising:
a channel connecting portion which connects lower portions of the first channel pattern and the second channel pattern and is in contact with the source pattern.
9 . The semiconductor memory device of claim 1 , wherein a concentration of hydrogen in the source pattern is higher than a concentration of hydrogen in the first channel pattern.
10 . A semiconductor memory device comprising:
bit lines disposed on a substrate and extending in a first direction in parallel to each other;
a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines;
a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer;
a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern;
a first channel pattern located on the source pattern;
a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines; and
a landing pad on the first channel pattern,
wherein a top surface of the first word line is located at a first level,
wherein the landing pad includes a protruding portion which extends toward the first channel pattern in a vertical direction and has the same width as the first channel pattern in the first direction, and
wherein a bottom surface of the protruding portion is located at a second level lower than the first level.
11 . The semiconductor memory device of claim 10 , wherein the hydrogen diffusion barrier layer has a single-layered or multi-layered structure of at least one of silicon nitride and aluminum oxide.
12 . The semiconductor memory device of claim 10 , wherein the first channel pattern penetrates the hydrogen diffusion barrier layer so as to be in contact with the source pattern.
13 . The semiconductor memory device of claim 10 , wherein a concentration of hydrogen in the source pattern is higher than a concentration of hydrogen in the first channel pattern.
14 . A semiconductor memory device comprising:
bit lines disposed on a substrate and extending in a first direction in parallel to each other;
a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines;
a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer;
a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern;
a first channel pattern located on the source pattern;
a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines;
a landing pad on the first channel pattern;
a second channel pattern which is located on the source pattern and is adjacent to the first channel pattern; and
a second word line which is located between the first word line and the second channel pattern and is closer to the second channel pattern than the first word line in the first direction.
15 . The semiconductor memory device of claim 14 , wherein the hydrogen diffusion barrier layer has a single-layered or multi-layered structure of at least one of silicon nitride and aluminum oxide.
16 . The semiconductor memory device of claim 14 , wherein the first channel pattern penetrates the hydrogen diffusion barrier layer so as to be in contact with the source pattern.
17 . The semiconductor memory device of claim 14 , further comprising:
a channel connecting portion which connects lower portions of the first channel pattern and the second channel pattern and is in contact with the source pattern.
18 . The semiconductor memory device of claim 14 , wherein a concentration of hydrogen in the source pattern is higher than a concentration of hydrogen in the first channel pattern.