Semiconductor device having contact field plate (CFP) and method for manufacturing the same

1 . A method for manufacturing a semiconductor device, comprising:

forming a gate oxide layer over an N-type well region and a P-type well region, wherein the gate oxide layer comprises an input/output (I/O) oxide layer portion and a reduced surface field oxide (ROX) layer portion;

forming a poly gate on the I/O oxide layer portion, wherein the poly gate extends along an interface between the N-type well region and the P-type well region;

forming at least one poly strap on the ROX layer portion;

forming a resist protect oxide (RPO) layer to completely cover the poly strap and partially cover the poly gate;

forming an inter-level dielectric (ILD) layer over the RPO layer; and

forming a first connecting feature penetrating the ILD layer and the RPO layer to contact the poly strap.

2 . The method of claim 1 , wherein a thickness ratio of the ROX layer portion to the I/O oxide layer portion is greater than 3.

3 . The method of claim 1 , further comprising:

conformally forming a contact etch stop layer to cover the P-type well region, the N-type well region, the RPO layer, and the poly gate non-covering by the RPO layer,

wherein the RPO layer is separated from the ILD layer by the contact etch stop layer.

4 . The method of claim 3 , wherein the first connecting feature is a contact field plate extending from an uppermost surface of the ILD layer into the poly strap through the contact etch stop layer and the RPO layer.

5 . The method of claim 1 , further comprising:

forming a source region in the P-type well region; and

forming a drain region in the N-type well region,

wherein the poly strap is electrically connected to the source region through the first connecting feature.

6 . The method of claim 5 , further comprising:

forming a plurality of second connecting features penetrating the ILD layer to the source region, the drain region and the poly gate.

7 . The method of claim 5 , further comprising:

forming salicide regions on a surface of the source region, a surface of the drain region and a surface of the poly gate non-covering by the RPO layer.

8 . The method of claim 1 , wherein the poly gate and the poly strap have the same thickness.

9 . The method of claim 1 , further comprising:

forming sidewall spacers on sidewalls of the poly gate and the poly strap,

wherein a width of the poly gate is greater than a width of the poly strap in a direction perpendicular to the interface between the N-type well region and the P-type well region.

10 . A method for manufacturing a semiconductor device, comprising:

forming an N-type well region in a substrate;

forming a P-type well region in the substrate;

forming a gate oxide layer over the substrate, wherein the gate oxide layer comprises a reduced surface field oxide (ROX) layer portion on the N-type well region and an input/output (I/O) oxide layer portion on the N-type well region and the P-type well region;

forming a poly gate on the I/O oxide layer portion and a plurality of poly straps on the ROX layer portion;

forming a resist protect oxide (RPO) layer to completely cover the poly straps;

forming a contact etch stop layer over the RPO layer; and

forming a plurality of first connecting features penetrating the contact etch stop layer and the RPO layer to contact the poly straps.

11 . The method of claim 10 , wherein the poly gate extends along a first axis parallel to an interface between the N-type well region and the P-type well region, and the poly straps are arranged in at least one line along the first axis.

12 . The method of claim 10 , wherein a thickness ratio of the ROX layer portion to the I/O oxide layer portion is greater than 3.

13 . The method of claim 10 , further comprising:

forming an inter-level dielectric (ILD) layer over the contact etch stop layer,

wherein each of the first connecting features is a contact field plate extending from an uppermost surface of the ILD layer into respective poly strap through the contact etch stop layer and the RPO layer.

14 . The method of claim 10 , further comprising:

forming a source region in the P-type well region; and

forming a drain region in the N-type well region,

wherein the poly straps are electrically connected to the source region through the first connecting features.

15 . The method of claim 14 , further comprising:

forming a plurality of second connecting features penetrating the contact etch stop layer to the source region, the drain region and the poly gate.

16 . A semiconductor device, comprising:

a gate oxide layer, comprising:

a reduced surface field oxide (ROX) layer portion on an N-type well region; and

an input/output (I/O) oxide layer portion on the N-type well region and a P-type well region, wherein the ROX layer portion is thicker than the I/O oxide layer portion;

a poly gate disposed on the I/O oxide layer portion and extending along an interface between the N-type well region and the P-type well region;

a plurality of poly straps disposed on the ROX layer portion;

a resist protect oxide (RPO) layer completely covering the poly straps;

a contact etch stop layer over the poly gate and the RPO layer; and

a plurality of contact field plate (CFP) features penetrating the contact etch stop layer and the RPO layer to contact the poly straps.

17 . The semiconductor device of claim 16 , further comprising:

a source region formed in the P-type well region; and

a drain region formed in the N-type well region,

wherein the poly straps are electrically connected to the source region through the CFP features.

18 . The semiconductor device of claim 17 , further comprising:

an inter-level dielectric (ILD) layer over the contact etch stop layer; and

a plurality of connecting features penetrating the ILD layer and the contact etch stop layer to the source region, the drain region and the poly gate.

19 . The semiconductor device of claim 16 , wherein the poly gate is partially covered by the RPO layer, and a salicide region is formed between the contact etch stop layer and the poly gate non-covering by the RPO layer.

20 . The semiconductor device of claim 16 , wherein the poly straps are arranged in an array from a top view, and the poly gate is longer than the poly straps.