Power device with low gate charge and low figure of merit
A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell.
1 . A method of fabricating a device cell, the method comprising:
forming only one instance of a structure on a main surface of the device cell, the structure having a first length;
forming a gate isolation layer on the main surface of the device cell over the structure having a second length at least twice as long as the first length, wherein the gate isolation layer is disposed over no more than the one instance of the structure, and wherein the structure comprises an unsegmented gate that is offset from a center of the device cell in a lateral direction toward a first side of the device cell;
forming a single source contact on a side of the device cell that is proximate to the unsegmented gate, wherein a second side of the device cell opposite the first side is free from any source contact;
forming a source metal layer over the gate isolation layer; and
forming a drain on a main bottom surface of the device cell, wherein the device cell is disposed in a laterally symmetric body between the main surface and the main bottom surface,
wherein the laterally symmetric body comprises a first column of a first doping type proximate to the unsegmented gate comprising the single source contact, a second column of the first doping type that is remote from the unsegmented gate, and a central zone of a second doping type opposite the first doping type between the first column and the second column,
wherein the second column comprises a body contact region having an upper surface vertically spaced below a bottom surface of the gate isolation layer,
wherein the source metal layer electrically connects the first column and the second column, and
wherein the unsegmented gate is formed asymmetrically with respect to the gate isolation layer in a lateral direction parallel to the main surface of the device cell.
2 . The method of claim 1 , wherein the single source contact is formed asymmetrically with respect to the gate isolation layer.
3 . The method of claim 1 , wherein forming the unsegmented gate comprises forming a minimum length gate.
4 . The method of claim 1 , wherein forming the unsegmented gate comprises forming a polysilicon gate.
5 . A method of forming a device comprising a device cell, wherein each cell comprises a body comprising a main top surface and a main bottom surface, the method comprising:
forming only one instance of an unsegmented gate on the main top surface of the device having a first length, wherein the unsegmented gate is offset from a center of the device cell in a lateral direction toward a first side of the device cell;
forming a gate insulation layer over the unsegmented gate having a second length at least twice as long as the first length, the gate insulation layer having a first portion directly over the unsegmented gate and a second portion directly over the main top surface of the body;
forming a single source contact on a side of the body that is proximate to the unsegmented gate, wherein a second side of the device cell opposite the first side is free from any source contact;
forming a source metal region over the gate insulation layer; and
forming a drain contact on the main bottom surface of the body,
wherein the body comprises an N-type epitaxial layer extending from the main top surface of the body to the main bottom surface of the body, a first P-type column disposed below the first portion of the gate insulation layer extending from the main top surface of the body and only partially into the N-type epitaxial layer, and a second P-type column disposed below the second portion of the gate insulation layer extending from the main top surface of the body and only partially into the N-type epitaxial layer, wherein the unsegmented gate is formed with lateral asymmetry with respect to the gate insulation layer in a lateral direction parallel to the main top surface, and wherein the body is formed with lateral symmetry,
wherein the first P-type column comprises the single source contact, and the source metal region electrically connects the first P-type column and the second P-type column, and
wherein the second P-type column comprises a body contact region having an upper surface vertically spaced below a bottom surface of the gate insulation layer.
6 . The method of claim 5 , wherein forming the single source contact comprises forming the single source contact with one of the first P-type column or the second P-type column.
7 . The method of claim 5 , wherein the single source contact is formed asymmetrically with respect to the gate insulation layer.
8 . The method of claim 5 , wherein the second length is at least three times as long as the first length.
9 . The method of claim 5 , wherein forming the unsegmented gate comprises forming a minimum length gate.
10 . The method of claim 5 , wherein forming the unsegmented gate comprises forming a polysilicon gate.
11 . A method of forming a device comprising a device cell, wherein each cell comprises a body comprising a main top surface and a main bottom surface, the method comprising:
forming only one instance of an unsegmented gate on the main top surface of the device having a first length, wherein the unsegmented gate is offset from a center of the device cell in a lateral direction toward a first side of the device cell;
forming a gate insulation layer over the unsegmented gate having a second length at least twice as long as the first length, the gate insulation layer having a first portion directly over the unsegmented gate and a second portion directly over the main top surface of the body;
forming a single source contact on a side of the body that is proximate to the unsegmented gate, wherein a second side of the device cell opposite the first side is free from any source contact;
forming a source metal region over the gate insulation layer; and
forming a drain contact on the main bottom surface of the body,
wherein the body comprises an N-type epitaxial layer extending from the main top surface of the body to the main bottom surface of the body between a first P-type column below the first portion of the gate insulation layer and a second P-type column below the second portion of the gate insulation layer, and wherein the unsegmented gate is formed with lateral asymmetry with respect to the gate insulation layer in a lateral direction parallel to the main top surface, and wherein the body is formed with lateral symmetry, and
wherein the first P-type column comprises the single source contact, and the source metal region electrically connects the first P-type column and the second P-type column, and
wherein the second P-type column comprises a body contact region having an upper surface vertically spaced below a bottom surface of the gate insulation layer.
12 . The method of claim 11 , wherein forming the single source contact comprises forming the single source contact with one of the first P-type column or the second P-type column.
13 . The method of claim 11 , wherein the single source contact is formed asymmetrically with respect to the gate insulation layer.
14 . The method of claim 11 , wherein the second length is at least three times as long as the first length.
15 . The method of claim 11 , wherein forming the unsegmented gate comprises forming a minimum length gate.
16 . The method of claim 11 , wherein forming the unsegmented gate comprises forming a polysilicon gate.
17 . The method of claim 1 , wherein the device cell comprises a vertical double-doped metal oxide semiconductor (VDMOS) transistor.
18 . The method of claim 5 , wherein the device comprises a vertical double-doped metal oxide semiconductor (VDMOS) transistor.
19 . The method of claim 11 , wherein the device comprises a vertical double-doped metal oxide semiconductor (VDMOS) transistor.
20 . The method of claim 1 , wherein the gate isolation layer has a curved upper surface profile that rises over the unsegmented gate.