Semiconductor device and method of manufacturing the same
An improved structure and a manufacturing method of a vertical type power MOSFET having a super junction configuration is disclosed. The improved structure and the manufacturing method of the vertical type power MOSFET comprising: a step of preparing a semiconductor substrate SB including an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL; a step of forming a trench GT in the p-type epitaxial layer EP by using an etching mask with a predetermined opening width; and a step of introducing an n-type impurity into a bottom portion of the trench GT using the etching mask with the predetermined opening width, whereby forming an n-type column NC at the bottom of trench GT and reaching the semiconductor layer SL.
1 . A method of manufacturing a semiconductor device, the method comprising:
(a) preparing a semiconductor substrate having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type;
(b) forming a gate trench having a predetermined width and reaching an intermediate depth from an upper surface of the second semiconductor layer by using an etching mask having a predetermined opening width;
(c) forming a first column of the first conductivity type in the second semiconductor layer by introducing an impurity of the first conductivity type into a bottom of the gate trench such that the first column reaches the first semiconductor layer; and
(d) forming a body region of the second conductivity type and a source region of the first conductivity type in the second semiconductor layer at a side surface of the gate trench,
wherein the introduction of the impurity of the first conductivity type in the (c) is performed by an ion implantation using the etching mask in the (b) defining an opening of the gate trench, and
wherein the first column is separated from a bottom surface of the gate trench.
2 . The method according to claim 1 ,
wherein in the (b), a plurality of gate trenches including the gate trench is formed in the second semiconductor layer, and
wherein a portion of the second semiconductor layer is formed between opposing side surfaces of two adjacent gate trenches.
3 . A method of manufacturing a semiconductor device, the method comprising:
(a) preparing a semiconductor substrate having a first semiconductor layer of a first conductivity type and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer;
(b) forming a gate trench having a predetermined width and reaching an intermediate depth from an upper surface of the second semiconductor layer by using an etching mask having a predetermined opening width;
(c) forming a first column of the first conductivity type in the second semiconductor layer by introducing an impurity of the first conductivity type into a bottom of the gate trench such that the first column reaches the first semiconductor layer;
(d) forming a body region of a second conductivity type and a source region of the first conductivity type in the second semiconductor layer at a side surface of the gate trench, the second conductivity type being different from the first conductivity type; and
(e) forming a second column of the second conductivity type in the second semiconductor layer by introducing an impurity of the second conductivity type into the second semiconductor layer such that the second column is spaced from the gate trench and is adjacent to the first column in a first direction along an upper surface of the second semiconductor layer,
wherein the introduction of the impurity of the first conductivity type in the (c) is performed by an ion implantation using the etching mask in the (b) defining an opening of the gate trench, and
wherein the first column is separated from a bottom surface of the gate trench.