Semiconductor device, method of manufacturing the semiconductor device, and electronic apparatus including the semiconductor device
View Patent ↗Disclosed are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a substrate; an active region extending vertically on the substrate, wherein the active region includes a first source/drain layer, a channel layer and a second source/drain layer that are sequentially stacked; a gate stack formed around at least part of an outer peripheral sidewall of the channel layer. A sidewall of the gate stack close to the channel layer is aligned with the outer peripheral sidewall of the channel layer, so as to occupy substantially a same range in a vertical direction, and a part of the gate stack close to the channel layer has a shape that gradually tapers as getting close to the channel layer.
1 . A semiconductor device, comprising:
a substrate;
an active region extending vertically on the substrate, wherein the active region comprises a first source/drain layer, a channel layer and a second source/drain layer that are sequentially stacked;
a gate stack formed around at least part of an outer peripheral sidewall of the channel layer, wherein the outer peripheral sidewall of the channel layer extends vertically,
wherein a sidewall of the gate stack closest to the channel layer is aligned with the outer peripheral sidewall of the channel layer, so as to occupy a same range in a vertical direction;
wherein the gate stack comprises a gate dielectric layer and a gate conductor layer formed on the gate dielectric layer, and each of a part of the gate dielectric layer close to the channel layer and a part of the gate conductor layer close to the channel layer has a shape that gradually increases firstly and then gradually decreases in the vertical direction as getting close to a sidewall of the gate stack closest to the channel layer in a horizontal direction;
wherein as getting close to the channel layer in the horizontal direction, each of a top surface of the gate conductor layer and a bottom surface of the gate conductor layer has a shape that gradually increases firstly and then gradually decreases in the vertical direction, and in a position where the gate stack is in contact with the channel layer, the gate conductor layer is aligned with the channel layer in the vertical direction; and
wherein the gate conductor layer comprises a hollow structure.
2 . The semiconductor device of claim 1 , wherein the part of the gate dielectric layer and the part of the gate conductor layer are located at an end portion of the gate stack close to the channel layer.
3 . The semiconductor device of claim 1 , wherein at least part of a surface of the gate stack extends substantially along a crystal plane direction of the channel layer.
4 . The semiconductor device according to claim 1 , wherein,
the first source/drain layer comprises a first sub-layer and a second sub-layer formed around an outer periphery of the first sub-layer,
the second source/drain layer comprises a third sub-layer and a fourth sub-layer formed around an outer periphery of the third sub-layer, and
the first sub-layer, the channel layer and the third sub-layer are substantially center-aligned in a vertical direction.
5 . The semiconductor device of claim 4 , wherein an outer peripheral sidewall of the first sub-layer and an outer peripheral sidewall of the third sub-layer are recessed inwardly with respect to the outer peripheral sidewall of the channel layer, and an outer peripheral sidewall of the second sub-layer and an outer peripheral sidewall of the fourth sub-layer protrude outwardly with respect to the outer peripheral sidewall of the channel layer.
6 . The semiconductor device of claim 5 , wherein the outer peripheral sidewall of the first sub-layer and the outer peripheral sidewall of the third sub-layer are substantially aligned in the vertical direction.
7 . The semiconductor device of claim 1 , further comprising:
a spacer formed above the gate stack.
8 . The semiconductor device of claim 1 , wherein the gate conductor layer comprises a gap inside the part of the gate conductor layer.
9 . A semiconductor device, comprising:
a substrate;
an active region extending vertically on the substrate, wherein the active region comprises a first source/drain layer, a channel layer and a second source/drain layer that are sequentially stacked;
a hard mask layer formed on a top of the active region, wherein the hard mask layer has an outer peripheral sidewall substantially aligned with an outer peripheral sidewall of the channel layer in a vertical direction; and
a gate stack formed around at least part of the outer peripheral sidewall of the channel layer, wherein the outer peripheral sidewall of the channel layer extends vertically, a sidewall of the gate stack closest to the channel layer is aligned with the outer peripheral sidewall of the channel layer, so as to occupy a same range in the vertical direction;
wherein the gate stack comprises a gate dielectric layer and a gate conductor layer formed on the gate dielectric layer, and each of an end portion of the gate dielectric layer close to the channel layer and an end portion of the gate conductor layer close to the channel layer has a shape that gradually increases firstly and then gradually decreases in the vertical direction as getting close to a sidewall of the gate stack closest to the channel layer in a horizontal direction,
wherein as getting close to the channel layer in the horizontal direction, each of a top surface of the gate conductor layer and a bottom surface of the gate conductor layer has a shape that gradually increases firstly and then gradually decreases in the vertical direction, and in a position where the gate stack is in contact with the channel layer, the gate conductor layer is aligned with the channel layer in the vertical direction; and
wherein the gate conductor layer comprises a hollow structure.
10 . The semiconductor device of claim 9 , wherein,
the first source/drain layer comprises a first sub-layer and a second sub-layer formed around an outer periphery of the first sub-layer,
the second source/drain layer comprises a third sub-layer and a fourth sub-layer formed around an outer periphery of the third sub-layer, and
the first sub-layer, the channel layer, the third sub-layer and the hard mask layer are substantially center-aligned in the vertical direction, an outer peripheral sidewall of the first sub-layer and an outer peripheral sidewall of the third sub-layer are recessed inwardly with respect to the outer peripheral sidewall of the hard mask layer, and an outer peripheral sidewall of the second sub-layer and an outer peripheral sidewall of the fourth sub-layer protrude outwardly with respect to the outer peripheral sidewall of the hard mask layer.
11 . The semiconductor device of claim 9 , further comprising:
a contact layer under the active region and connected with the first source/drain layer, wherein the contact layer extends beyond the outer peripheral sidewall of the hard mask layer.
12 . The semiconductor device of claim 9 , wherein the end portion of the gate stack close to the channel layer has a shape that first gradually increases and then gradually decreases as getting close to the channel layer.
13 . The semiconductor device of claim 9 , wherein at least part of a surface of the end portion of the gate stack close to the channel layer extends substantially along a crystal plane direction of the channel layer.
14 . The semiconductor device of claim 12 , wherein the gate conductor layer comprises a gap inside the end portion.
15 . An electronic apparatus, comprising an integrated circuit formed at least partially by the semiconductor device of claim 1 .
16 . The electronic apparatus of claim 15 , further comprising:
a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.
17 . The electronic apparatus of claim 15 , wherein the electronic apparatus comprises a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device, or a mobile power supply.