Square-shaped contact with improved electrical conductivity
An approach provides a semiconductor structure with one or more rectangular or square-shaped contact vias in a semiconductor material. The semiconductor device includes one of the first element of the semiconductor device element under the square-shaped contact via or the second element of the semiconductor device element above the square-shaped contact via. The semiconductor structure includes the square-shaped via in the semiconductor material that has straight edges that are parallel to one or more of the (110) crystal planes of the semiconductor material and the square-shaped contact vias has corners pointing in a direction orthogonal to one or more of the (100) crystal planes of the semiconductor material. The square-shaped contact via provides a larger contact area that a conventional round-shaped contact via with a diameter matching the width of the square-shaped contact via.
1 . A semiconductor structure comprising:
a rectangular-shaped via in a semiconductor material, wherein:
the rectangular-shaped via directly contacts: (i) a source/drain and (ii) a power rail;
the rectangular-shaped via has a total of six sides;
the rectangular-shaped via tapers such that a first surface contacting the source/drain has a smaller surface area than a second surface contacting the power rail; and
the first surface is planar; and
a dielectric liner surrounding tapered sides of the rectangular-shaped via, wherein a surface of the dielectric liner directly contacts the power rail and the surface of the dielectric liner is coplanar with the second surface.
2 . The semiconductor structure of claim 1 , wherein the rectangular-shaped via contacts a rectangular-shaped portion of the source/drain and a rectangular-shaped portion of the power rail.
3 . The semiconductor structure of claim 1 , wherein the power rail is a backside power rail.
4 . The semiconductor structure of claim 2 , wherein the source/drain is on a selection from the group consisting of: a backside of a semiconductor device and a frontside of the semiconductor device.
5 . A semiconductor structure comprising:
a square-shaped contact via in a semiconductor material of a semiconductor device, wherein the square-shaped contact via has a total of six sides;
a first semiconductor device element under the square-shaped contact via; and
a second semiconductor device element above the square-shaped contact via, wherein:
the square-shaped contact via tapers such that a first surface contacting the first semiconductor device element has a smaller surface area than a second surface contacting the second semiconductor device element; and
the first surface is planar.
6 . The semiconductor structure of claim 5 , wherein the square-shaped contact via in the semiconductor material has straight edges that are parallel to one or more (110) crystal planes of the semiconductor material.
7 . The semiconductor structure of claim 5 , wherein the square-shaped contact via in the semiconductor material has corners pointing in a direction orthogonal to one or more of (100) crystal planes of the semiconductor material.
8 . The semiconductor structure of claim 5 , wherein the first semiconductor device element is a source/drain of the semiconductor device.
9 . The semiconductor structure of claim 5 , wherein the second semiconductor device element is a pad in an interconnect wiring layer.
10 . The semiconductor structure of claim 5 , wherein the semiconductor device is selected from the group consisting of: a logic device, a memory device, and a photovoltaic device.
11 . The semiconductor structure of claim 5 , wherein the semiconductor device is a nanosheet transistor.
12 . The semiconductor structure of claim 8 , wherein the source/drain is on a backside of a nanosheet transistor.
13 . The semiconductor structure of claim 12 , wherein the source/drain is on a backside of the nanosheet transistor and connects to a backside power rail by the square-shaped contact via, further comprising:
a dielectric layer with at least one via over the backside power rail; and
a back end of line interconnect wiring layer connecting, by the at least one via, to the backside power rail.
14 . A method comprising:
patterning a top surface of a first layer of dielectric material on a semiconductor material for a first contact via hole;
etching the first contact via hole through the first layer of dielectric material and through a semiconductor layer, wherein the first contact via hole has a round shape;
performing a wet ammonia etching process on the first contact via hole to form a second contact via hole in the semiconductor material, wherein the second contact via hole has a rectangular shape;
removing the first layer of dielectric material on the semiconductor material;
depositing a layer of a contact material over the semiconductor material and in the second contact via hole; and
depositing and planarizing a contact metal to form a rectangular-shaped contact via, wherein:
the rectangular-shaped contact via has a total of six sides;
the rectangular-shaped contact via tapers such that a first surface contacting the semiconductor material has a smaller surface area than a second surface;
the first surface is planar; and
the second surface is a surface of the contact metal exposed as a result of planarizing the contact metal.
15 . The method of claim 14 , wherein the semiconductor material is a silicon material.
16 . The method of claim 14 , wherein performing the wet ammonia etching process on the first contact via hole to form the second contact via hole in the semiconductor material further comprises:
a minimal etching of the semiconductor material in a direction of one or more (110) crystal planes of the semiconductor material; and
a rapid etching of the semiconductor material in the direction of one or more (100) crystal planes of the semiconductor material.
17 . The method of claim 14 , wherein removing the first layer of dielectric material on the semiconductor material, further comprises removing an exposed portion of a second dielectric material below the second contact via hole, wherein removing the exposed portion of the second dielectric material occurs on a portion of a source/drain on a backside of a nanosheet transistor.