Semiconductor device with enhanced mobility and method of forming the same
A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.
1 . A method of forming a semiconductor device, comprising:
forming a gate electrode within an insulating layer that overlies a substrate;
forming a gate dielectric layer over the gate electrode;
forming a semiconductor channel layer over the gate dielectric layer;
forming a dielectric layer over the semiconductor channel layer;
patterning the dielectric layer and the semiconductor channel layer, so as to form first and second openings that expose portions of the gate dielectric layer, wherein bottom surfaces of the first and second openings are substantially flush with a top surface of the gate dielectric layer;
forming an interfacial layer conformally on sidewalls and bottoms of the first and second openings, wherein the gate dielectric layer is a single layer, the top surface of the gate dielectric layer is in physical contact with the interfacial layer, and a bottom surface of the gate dielectric layer is in physical contact with the gate electrode;
forming a semiconductor layer over the interfacial layer in the first and second openings; and
forming a metal layer over the semiconductor layer in the first and second openings.
2 . The method of claim 1 , wherein the interfacial layer is in physical contact with the semiconductor layer.
3 . The method of claim 1 , wherein the interfacial layer comprises TiN, WCN, W, TaN, Ru, Al, InO, IZO, ITO or a combination thereof.
4 . The method of claim 1 , wherein the semiconductor layer is more conductive than the semiconductor channel layer, and the semiconductor layer and the semiconductor channel layer have a carrier density of about 1×10 14 /cm 3 or more.
5 . The method of claim 4 , wherein the semiconductor channel layer has a carrier density ranging from about 1×10 14 /cm 3 to 1×10 18 /cm 3 , and the semiconductor layer has a carrier density of about 1×10 19 /cm 3 or more.
6 . The method of claim 1 , further comprising forming a blocking layer between the gate dielectric layer and the semiconductor channel layer.
7 . The method of claim 6 , wherein the blocking layer comprises hafnium oxide, zirconium oxide, gallium oxide, tungsten oxide, aluminum oxide, silicon oxide, or a combination thereof.
8 . The method of claim 1 , further comprising performing a plasma treatment after forming the gate dielectric layer and before forming the semiconductor channel layer.
9 . The method of claim 8 , wherein the plasma treatment comprises ozone, O 2 , N 2 O, NH 3 , N 2 or a combination thereof.
10 . A method of forming a semiconductor device, comprising:
forming a gate electrode within an insulating layer that overlies a substrate;
forming a gate dielectric layer over the gate electrode;
forming a blocking layer on the gate dielectric layer;
forming a semiconductor channel layer over the blocking layer;
forming a dielectric layer over the semiconductor channel layer;
patterning the dielectric layer, the semiconductor channel layer and the blocking layer, so as to form first and second openings that expose portions of the gate dielectric layer, wherein bottom surfaces of the first and second openings are substantially flush with a top surface of the gate dielectric layer;
forming an interfacial layer in the first and second openings, wherein the gate dielectric layer is a single layer, the top surface of the gate dielectric layer is in physical contact with the interfacial layer, and a bottom surface of the gate dielectric layer is in physical contact with the gate electrode;
forming a semiconductor layer in the first and second openings; and
forming a metal layer over the semiconductor layer in the first and second openings.
11 . The method of claim 10 , wherein the blocking layer comprises hafnium oxide, zirconium oxide, gallium oxide, tungsten oxide, aluminum oxide, silicon oxide, or a combination thereof.
12 . The method of claim 10 , wherein the semiconductor layer is more conductive than the semiconductor channel layer.
13 . The method of claim 10 , wherein the semiconductor layer is formed on the interfacial layer such that the interfacial layer covers a bottom surface and sidewalls of the semiconductor layer.
14 . The method of claim 13 , wherein the interfacial layer comprises TiN, WCN, W, TaN, Ru, Al, InO, IZO, ITO or a combination thereof.
15 . A method of forming a semiconductor device, comprising:
forming a gate electrode within an insulating layer over a transistor;
forming a gate dielectric layer over the gate electrode;
forming a semiconductor channel layer over the gate dielectric layer;
forming a dielectric layer over the semiconductor channel layer;
forming first and second openings in the dielectric layer and the channel semiconductor layer, wherein bottom surfaces of the first and second openings are substantially flush with a top surface of the gate dielectric layer;
forming an interfacial layer in the first and second openings, wherein the gate dielectric layer is a single layer, the top surface of the gate dielectric layer is in physical contact with the interfacial layer, and a bottom surface of the gate dielectric layer is in physical contact with the gate electrode;
forming a semiconductor layer in the first and second openings; and
forming a metal layer over the semiconductor layer in the first and second openings.
16 . The method of claim 15 , wherein the interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings.
17 . The method of claim 15 , wherein the semiconductor layer is more conductive than the semiconductor channel layer.
18 . The method of claim 15 , further comprising forming a blocking layer between the gate dielectric layer and the semiconductor channel layer.
19 . The method of claim 15 , further comprising performing a plasma treatment after forming the gate dielectric layer and before forming the semiconductor channel layer.
20 . The method of claim 15 , further comprising forming a memory cell electrically connected to the metal layer.