Transistor, semiconductor device, and semiconductor structure with 2D intermediate contact pattern
A transistor includes a gate structure, a spacer laterally surrounding the gate structure. a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, and a source/drain contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer.
1 . A transistor, comprising:
a gate structure;
a spacer laterally surrounding the gate structure;
a channel layer underlying the gate structure and comprising a two-dimensional (2D) material;
a source/drain (S/D) contact laterally separated from the gate structure by the spacer and laterally coupled to the channel layer; and
an intermediate contact pattern laterally adjoining the channel layer and disposed below the spacer and the gate structure, wherein the S/D contact is laterally coupled to the channel layer through the intermediate contact pattern, and the intermediate contact pattern comprises a different 2D material than the 2D material of the channel layer.
2 . The transistor of claim 1 , further comprising:
a capping dielectric layer disposed on the gate structure, wherein the spacer extends along the gate structure and the capping dielectric layer.
3 . The transistor of claim 1 , wherein the gate structure is in direct contact with the intermediate contact pattern and the channel layer.
4 . The transistor of claim 1 , wherein an interface of the channel layer and the intermediate contact pattern is disposed below the gate structure.
5 . The transistor of claim 1 , wherein the S/D contact comprises a first contact material layer laterally adjoining the intermediate contact pattern and a second contact material layer disposed on the first contact material layer.
6 . The transistor of claim 5 , wherein the first contact material layer of the S/D contact is thicker than the intermediate contact pattern.
7 . The transistor of claim 5 , wherein the second contact material is laterally surrounded by the first contact material layer.
8 . The transistor of claim 5 , further comprising:
a contact etch stop layer laterally surrounding the first contact material layer of the S/D contact.
9 . The transistor of claim 1 , further comprising:
an insulating pattern interposed between the gate structure and the intermediate contact pattern.
10 . A semiconductor structure, comprising:
a semiconductor substrate;
a transistor disposed over the semiconductor substrate and comprising:
a gate structure;
a channel layer underlying the gate structure and comprising a first 2D material;
a S/D contact laterally coupled to the channel layer;
an intermediate contact pattern underlying the gate structure and laterally coupling the channel layer to the S/D contact, and the intermediate contact pattern comprising a second 2D material different from the first 2D material; and
a bottom dielectric layer overlying the semiconductor substrate and separating the channel layer from the semiconductor substrate.
11 . The semiconductor device of claim 10 , wherein a bottom surface of the gate structure is substantially planar and is in direct contact with the channel layer.
12 . The semiconductor device of claim 10 , further comprising:
an interconnect structure disposed over the semiconductor substrate, a dielectric layer of the interconnect structure covering the transistor, and a metallization pattern of the interconnect structure being electrically coupled to the transistor.
13 . The semiconductor device of claim 10 , wherein the transistor further comprises:
a spacer disposed on the intermediate contact pattern and extending along a sidewall of the gate structure.
14 . The semiconductor structure of claim 10 , wherein an inner portion of the gate structure overlaps the channel layer and an outer portion of the gate structure overlaps the intermediate contact pattern.
15 . The semiconductor structure of claim 10 , wherein the transistor further comprises:
an insulating pattern interposed between the gate structure and the intermediate contact pattern.
16 . The semiconductor structure of claim 10 , wherein the S/D contact comprises a first contact material layer laterally coupled to the channel layer intermediate contact pattern and a second contact material layer overlying the first contact material layer, and the first contact material layer is wider than the second contact material layer.
17 . A semiconductor device, comprising:
a gate structure;
a S/D contact laterally spaced apart from the gate structure;
a channel layer underlying an inner portion of the gate structure; and
an intermediate contact pattern underlying an outer portion of the gate structure and laterally encircling the channel layer, wherein the intermediate contact pattern is laterally connected to the S/D contact and comprises a first 2D material, and an interface is present between the channel layer and the intermediate contact pattern.
18 . The semiconductor device of claim 17 , wherein the channel layer comprises a second 2D material different from the first 2D material.
19 . The semiconductor device of claim 17 , wherein a maximum lateral dimension of the gate structure is greater than that of the channel layer.
20 . The semiconductor device of claim 17 , wherein the outer portion of the gate structure is in direct contact with the intermediate contact pattern.