Ultra-steep slope and high-performance strain effect transistor
Embodiments relate to a transistor having a substrate and a gate formed in or on a surface of the substrate. The gate can include a piezoelectric material. The transistor has a drain and a source formed in or on a surface of the gate. The transistor has a channel formed adjacent to the gate and located between the drain and the source. The channel can include a semiconductor/semi-metallic material. The transistor can have a source contact formed at the source and configured to anchor the semiconductor/semi-metallic channel material to the piezoelectric material. The transistor can have a drain contact formed at the drain and configured to anchor the semiconductor/semi-metallic channel material to the piezoelectric material. The transistor operates on the principle of voltage induced strain transduction via a piezoelectric gate stack leading to a modification of the interface between the metal contact and the semiconducting/semi-metallic channel material.
1 . A transistor, comprising:
a substrate;
a gate formed in or on a surface of the substrate, the gate comprising a piezoelectric material;
a drain and a source, each of the drain and the source formed in or on a surface of the gate;
a channel formed in or on a surface of the gate, the channel located between the drain and the source, the channel comprising a semiconducting/semi-metallic material;
a source contact region comprising a transistor layer stack in which a source contact is vertically aligned with the source, the channel, and the gate, the source contact being formed at the source and configured to anchor the semiconducting/semi-metallic material to the piezoelectric material via mechanical or chemical adhesion between the semiconducting/semi-metallic material and the piezoelectric material;
a drain contact region comprising a transistor layer stack in which a drain contact is vertically aligned with the drain, the channel, and the gate, the drain contact being formed at the drain and configured to anchor the semiconducting/semi-metallic material to the piezoelectric material via mechanical or chemical adhesion between the semiconducting/semi-metallic material and the piezoelectric material;
wherein strain induced transduction in the gate causes contact modification between the channel and the source contact and between the channel and the drain contact;
wherein such that strain transduction is limited to the channel material within the source contact region and the drain contact region due to: the anchoring by the source contact and drain contact; and tensile strength of the source contact material and the drain contact material.
2 . The transistor of claim 1 , wherein:
an out-of-plane direction is defined by a vertical direction through the substrate, the gate, and the channel;
an in-plane direction is defined as a horizontal direction perpendicular to the out-of-plane direction; and
an electric field applied to the gate generates an out-of-plane strain on the piezoelectric material which causes the contact modification.
3 . The transistor of claim 1 , wherein the contact modification involves cracking/delamination at the interface between the channel and the source contact material and/or the drain contact material or a conductor to insulator phase transition at the interface between the channel and the source contact material and/or the drain contact material.
4 . The transistor of claim 2 , wherein:
the substrate forms a second gate and the second gate is connected to a gate-to-source voltage (V GS );
the drain is connected to a drain-to-source voltage (V DS );
the source is connected to ground; and
V GS >0 applies an electric field to the gate.
5 . The transistor of claim 2 , wherein an electric field greater than a threshold value is required to generate contact modification.
6 . The transistor of claim 5 , wherein Vas greater than or equal to a threshold value (V GS > or =V S ) generates the electric field greater than the threshold value to cause the contact modification.
7 . The transistor of claim 6 , wherein:
when V GS <V S , the transistor is in an ON state; and
when V GS > or =V S , the transistor is in an OFF state.
8 . The transistor of claim 1 , wherein the substrate is a conducting material or a degenerately doped semiconducting material.
9 . The transistor of claim 1 , wherein the piezoelectric material is lead zirconate titanate (PZT).
10 . The transistor of claim 1 , wherein the piezoelectric material has a thickness of 2 micrometers (μm).
11 . The transistor of claim 1 , wherein the channel material is a voltage induced strain transduction material.
12 . The transistor of claim 1 , wherein the channel material is a semiconducting/semi-metallic material.
13 . The transistor of claim 1 , wherein the transistor exhibits contact modification at room temperature.
14 . The transistor of claim 1 , wherein the channel comprises IT′ MoTe 2 or graphene.