Silicon super junction structures for increased voltage
A super junction device with an increased voltage rating may be formed by decreasing the width of the P-type region and increasing the doping concentration, while also increasing the height of the overall device. However, instead of etching a trench in the N-type material to fill with the P-type material, a trench may be etched for both the P-type region and an adjacent N-type region. This allows the height of the overall device to be increased while maintaining a feasible aspect ratio for the trench. The P-type material may then be formed as a sidewall liner on the trench that is relatively thin compared to the remaining width of the trench. The trench may then be filled with N-type material such that the P-type region fills the space between the N-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the P-type region alone.
1 . A super junction device comprising:
a first N-type region extending orthogonally up from a substrate, wherein the substrate forms a first contact region for the device;
a second N-type region extending orthogonally up from the substrate to a second contact region of the device; and
a P-type region extending orthogonally up from the substrate to a third contact region of the device, wherein the P-type region is disposed between the first N-type region and the second N-type region, and a width of the P-type region comprises less than or about 10% of a combined width of the P-type region and the second N-type region.
2 . The super junction device of claim 1 , wherein a height of the P-type region is greater than or about 70 μm.
3 . The super junction device of claim 1 , wherein the width of the P-type region is less than or about 200 nm.
4 . The super junction device of claim 1 , wherein:
the first contact region comprises a drain of a super junction transistor;
the second contact region comprises a gate of the super junction transistor; and
the third contact region comprises a source of the super junction transistor.
5 . The super junction device of claim 4 , wherein the super junction transistor has a breakdown voltage of greater than or about 1200 V.
6 . The super junction device of claim 1 , wherein the combined width of the P-type region and the second N-type region is less than or about 4 μm.
7 . The super junction device of claim 1 , wherein a doping concentration of the P-type region is higher than a doping concentration of the second N-type region.
8 . A super junction device comprising:
a silicon substrate forming a drain region for the device;
a gate region;
a source region;
an N-type region extending from the silicon substrate up to the gate region; and
a P-type region extending from the silicon substrate up to the source region, wherein the device has a breakdown voltage of greater than or about 1000 V, and a doping concentration of the P-type region is greater than about 8 times the doping concentration of the N-type region.
9 . The super junction device of claim 8 , wherein a height of the N-type region is about 80 μm.
10 . The super junction device of claim 8 , wherein an aspect ratio of an area occupied by the N-type region and the P-type region is less than or about 20.
11 . The super junction device of claim 8 , wherein a width of an area occupied by the N-type region and the P-type region is less than or about 4 μm.
12 . A method of forming a super junction device, the method comprising:
forming a first N-type material on a substrate, wherein the first N-type material has a height of greater than or about 70 μm above the substrate;
etching a trench in the first N-type material, wherein the trench extends from a top surface of the first N-type material down to at least a top surface of the substrate to form a first N-type region;
forming a P-type liner on a sidewall portion of the first N-type region in the trench, wherein the P-type liner is less than or about 300 nm;
filling the trench with an N-type material to form a second N-type region such that the P-type liner is between the first N-type region and the second N-type region.
13 . The method of claim 12 , wherein the trench is etched below the top surface of the substrate.
14 . The method of claim 12 , further comprising forming a passivation layer over the P-type liner.
15 . The method of claim 14 , further comprising removing the passivation layer before filling the trench.
16 . The method of claim 12 , wherein the P-type liner is also formed on a bottom of the trench.
17 . The method of claim 16 , further comprising performing a directional etch to remove the P-type liner from the bottom of the trench while leaving the P-type liner along the sidewall portion of the trench.
18 . The method of claim 12 , wherein a width of the area occupied by the first N-type region and the P-type liner is less than or about 4 μm.
19 . The method of claim 12 , wherein a doping concentration of the first N-type region is between about 1e14 dopants/cm 3 and about 1e16 dopants/cm 3 .
20 . The method of claim 19 , wherein a doping concentration of the P-type liner is greater than about 8 times the doping concentration of the first N-type region.