IP Library Granted Patent US 12713665
Granted Patent B2
US 12713665 · App. 17/985,489 · Granted Aug 18, 2026

Super-junction semiconductor device with enlarged process window for desirable breakdown voltage

Inventors: Lvqiang Li (Hangzhou City, CN); Hui Chen (Hangzhou City, CN); Jiakun Wang (Hangzhou City, CN)
Assignee: SILICON-MAGIC SEMICONDUCTOR TECHNOLOGY (HANGZHOU) CO., LTD.
H10D62/111H10D62/822H10D62/8303H10D62/8325
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Quick Facts
Patent No.
US 12713665
App. No.
17/985,489
Granted
Aug 18, 2026
Kind
B2
Abstract

A super-junction semiconductor device with an enlarged process window for a desirable breakdown voltage includes: a semiconductor substrate and an epitaxial layer deposited on the semiconductor substrate. The epitaxial layer includes a first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer. A band gap of the first semiconductor layer is greater than a band gap of the second semiconductor layer. A super-junction structure is formed in the epitaxial layer, including at least one first epitaxial pillar of a first dopant type, and at least one second epitaxial pillar of a second dopant type. The first epitaxial pillar and the second epitaxial pillar are alternately arranged along a transverse direction. The epitaxial layer has a sandwich structure.

Claims (18)

1 . A super-junction semiconductor device with an enlarged process window comprising:

a semiconductor substrate;

an epitaxial layer disposed on the semiconductor substrate,

wherein the epitaxial layer comprises a first semiconductor layer, a second semiconductor layer disposed on an upper surface of the first semiconductor layer, and a third semiconductor layer disposed on the lower surface of the first semiconductor layer,

wherein a band gap of the first semiconductor layer is greater than a band gap of the second semiconductor layer and a band gap of the third semiconductor layer; and

a super-junction structure formed in the epitaxial layer,

wherein the super-junction structure comprises at least one first epitaxial pillar of a first dopant type and at least one second epitaxial pillar of a second dopant type,

wherein the first epitaxial pillar and the second epitaxial pillar are alternately arranged along a transverse direction,

wherein the super-junction structure extends downwardly from an upper surface of the second semiconductor layer to a lower surface of the third semiconductor layer, and

wherein the first dopant type is opposite to the second dopant type.

2 . The super-junction semiconductor device of claim 1 , wherein the semiconductor substrate is a silicon substrate, the first semiconductor layer comprises silicon carbide or diamond, the second semiconductor layer comprises silicon, and the third semiconductor layer comprises silicon.

3 . The super-junction semiconductor device of claim 2 , wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer, and is greater than a thickness of the third semiconductor layer.

4 . The super-junction semiconductor device of claim 1 , wherein the first epitaxial pillar and the second epitaxial pillar are complementary inclined pillars.

5 . The super-junction semiconductor device of claim 1 , wherein the first dopant type is N type or P type, and the second dopant type is P type or N type.

6 . A super-junction diode comprising the super-junction semiconductor device of claim 1 .

7 . An insulated gate bipolar transistor comprising the super-junction semiconductor device of claim 1 .

8 . A vertical double-diffused metal oxide semiconductor device comprising the super-junction semiconductor device of claim 1 .

9 . The super-junction semiconductor device of claim 1 , wherein the first epitaxial pillar and the second epitaxial pillar are comprised in each of the first semiconductor layer and the second semiconductor layer.