Dielectric structure and substrate processing apparatus including the same
A dielectric structure may include: an insulating layer extending in a first direction; a plurality of conductor layers disposed on a first surface of the insulating layer and spaced apart from each other in the first direction; at least one semiconductor layer disposed on a second surface of the insulating layer, opposite to the first surface, and overlapping each of at least two conductor layers adjacent to each other among the plurality of conductor layers in a second direction intersecting the first direction; a first protective layer covering the plurality of conductor layers on the first surface of the insulating layer; and a second protective layer covering the at least one semiconductor layer on the second surface of the insulating layer.
1 . A plasma asymmetry control structure comprising:
a plurality of dielectric structures, each of the plurality of dielectric structures comprising
an insulating layer extending in a first direction;
a plurality of conductor layers disposed on a first surface of the insulating layer such that the plurality of conductor layers are spaced apart from each other in the first direction;
at least one semiconductor layer on a second surface of the insulating layer, opposite to the first surface, and overlapping each of at least two adjacent conductor layers, among the plurality of conductor layers, in a second direction intersecting the first direction;
a first protective layer covering the plurality of conductor layers on the first surface of the insulating layer; and
a second protective layer covering the at least one semiconductor layer on the second surface of the insulating layer, and
wherein the plurality of dielectric structures are parallel to each other such that the first protective layer of at least one of the plurality of dielectric structures faces the second protective layer of a neighboring one of the plurality of dielectric structures.
2 . The plasma asymmetry control structure of claim 1 , wherein a planar area of a plane of the at least one semiconductor layer, with a normal line extending in the second direction, overlaps with the at least two adjacent conductor layers at about 30% to about 99%.
3 . The plasma asymmetry control structure of claim 1 , wherein the at least one semiconductor layer has a first width in the first direction and overlaps each of the at least two adjacent conductor layers with a second width less than the first width.
4 . The plasma asymmetry control structure of claim 3 , wherein the first width is within a range of about 400 μm to about 1000 μm.
5 . The plasma asymmetry control structure of claim 3 , wherein the second width is about 15% or more of the first width.
6 . The plasma asymmetry control structure of claim 1 , wherein the at least one semiconductor layer includes at least one of germanium (Ge), silicon (Si), gallium arsenic (GaAs), indium nitride (InN), silicon carbide (SiC), gallium nitride (GaN), or aluminum nitride (AlN).
7 . The plasma asymmetry control structure of claim 1 , wherein the at least one semiconductor layer has a width greater than a first distance between the at least two adjacent conductor layers.
8 . The plasma asymmetry control structure of claim 7 , wherein the first distance is within a range of about 40 μm to about 100 μm.
9 . The plasma asymmetry control structure of claim 1 , wherein the plurality of conductor layers and the at least one semiconductor layer are spaced apart from each other by a second distance in the second direction,
wherein the second distance is about 3 μm to about 10 μm.
10 . The plasma asymmetry control structure of claim 1 , wherein a thickness of the plurality of conductor layers in the second direction is less than or equal to a thickness of the at least one semiconductor layer in the second direction.
11 . The plasma asymmetry control structure of claim 1 , wherein the plurality of conductor layers include at least one of aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or combinations thereof.
12 . The plasma asymmetry control structure of claim 1 , wherein the insulating layer, the first protective layer, and the second protective layer each include a light-transmitting material.
13 . A plasma shower head comprising:
a plurality of dielectric structures arranged to define a plurality of holes such that the plurality of holes extend in a first direction, each of the plurality of dielectric structures comprising
an insulating layer;
a plurality of conductor layers disposed on a first surface of the insulating layer such that the plurality of conductor layers are spaced apart from each other by a first distance in the first direction;
at least one semiconductor layer between at least two adjacent conductor layers, among the plurality of conductor layers, and on a second surface of the insulating layer, opposite to the first surface, the at least one semiconductor layer having a width greater than the first distance in the first direction;
a first protective layer covering the plurality of conductor layers on the first surface of the insulating layer; and
a second protective layer covering the at least one semiconductor layer on the second surface of the insulating layer, and
wherein the plurality of dielectric structures are parallel to each other such that the first protective layer of at least one of the plurality of dielectric structures faces the second protective layer of a neighboring one of the plurality of dielectric structures.
14 . A plasma asymmetry control structure comprising:
a plurality of dielectric structures, each of the plurality of dielectric structures comprising
an insulating layer;
a plurality of conductor layers disposed on a first surface of the insulating layer such that the plurality of conductor layers are spaced apart from each other in a first direction;
at least one semiconductor layer disposed on a second surface of the insulating layer, opposite to the first surface, and overlapping at least two adjacent conductor layers, among the plurality of conductor layers, in a second direction perpendicular to the first direction such that the at least one semiconductor layer and the at least two adjacent conductor layers are configured to form an internal electrical field when an external electric field is applied in the first direction; and
a first protective layer and a second protective layers covering the plurality of conductor layers and the at least one semiconductor layer on the first surface and the second surface of the insulating layer, respectively, and
wherein the plurality of dielectric structures are parallel to each other such that the first protective layer of at least one of the plurality of dielectric structures faces the second protective layer of a neighboring one of the plurality of dielectric structures.
15 . The plasma asymmetry control structure of claim 14 , wherein the at least one semiconductor layer comprises semiconductor portions overlapping the at least two adjacent conductor layers, respectively, and a connection portion connecting the semiconductor portions.
16 . The plasma asymmetry control structure of claim 14 , wherein the second protective layer on the second surface is a light-transmitting substrate thicker than the first protective layer on the first surface, and
the at least one semiconductor layer is embedded in the second surface of the insulating layer.
17 . The plasma asymmetry control structure of claim 16 , wherein the light-transmitting substrate includes at least one of fused silica or sapphire.
18 . The plasma asymmetry control structure of claim 16 , wherein the plurality of conductor layers is embedded in the first surface of the insulating layer.
19 . The plasma asymmetry control structure of claim 14 , further comprising:
an upper insulating layer on the first protective layer;
an optical adhesive film between the first protective layer and the upper insulating layer;
at least one upper conductor layer on an upper surface of the upper insulating layer; and
an upper protective layer covering the at least one upper conductor layer on the upper surface of the upper insulating layer.
20 . The plasma asymmetry control structure of claim 19 , wherein the at least one upper conductor layer overlaps the at least two adjacent conductor layers and the at least one semiconductor layer in the second direction.