Backside contact with full wrap-around contact
A semiconductor device includes a source/drain having a height, a length, and a width. A full wrap-around contact surrounds a partial length of the source/drain, wherein the full wrap-around contact includes a partial front-side wrap-around contact from a front side of a substrate and a partial back-side wrap-around contact from a back side of the substrate.
1 . A semiconductor device, comprising:
a source/drain having a height, a length, and a width; and
a full wrap-around contact surrounding at least a partial length of the source/drain, wherein the full wrap-around contact includes a partial front-side wrap-around contact from a front side of a substrate and a partial back-side wrap-around contact from a back side of the substrate, wherein the partial back-side wrap-around contact is directly on a backside surface of the source/drain.
2 . The semiconductor device of claim 1 , wherein at least a portion of the full wrap-around contact comprises a metal-silicide layer on the source/drain and extending over insulating sidewalls adjacent the source/drain.
3 . The semiconductor device of claim 2 , wherein a portion of the metal-silicide layer separates the partial front-side wrap-around contact from the source/drain.
4 . The semiconductor device of claim 3 , further comprising one or more semiconductor nanosheet layer segments adjoining the source/drain.
5 . The semiconductor device of claim 4 , wherein a portion of the partial back-side wrap-around contact extends in a gap between a first interlayer dielectric layer and the source/drain.
6 . The semiconductor device of claim 5 , further comprising a replacement metal gate structure on the one or more semiconductor nanosheet layer segments, and an inner spacer separating the replacement metal gate structure from the source/drain.
7 . The semiconductor device of claim 6 , wherein the metal-silicide layer comprises nickel platinum silicide (NiPtSi).
8 . A backside power connection device, comprising:
a back-end-of-line metallization layer on a carrier wafer;
an interlevel dielectric layer on the back-end-of-line metallization layer;
a source/drain contact in the interlevel dielectric layer, and in electrical contact with the back-end-of-line metallization layer;
a source/drain electrically connected to the source/drain contact;
a replacement metal gate structure electrically separated from the source/drain;
a metal-silicide layer on the source/drain;
a backside interlevel dielectric layer; and
a backside conductive contact extending through an opening in the backside interlevel dielectric layer, the opening exposing a backside of the source/drain, the backside conductive contact being on and in electrical contact with the source/drain and the metal-silicide layer.
9 . The backside power connection device of claim 8 , further comprising a backside via on and in electrical contact with the backside conductive contact, a backside power rail on and in electrical contact with the backside via, and a backside power delivery network (BSPDN) on and to the backside power rail.
10 . The backside power connection device of claim 8 , further comprising one or more semiconductor nanosheet layer segments adjoining the source/drain.
11 . The backside power connection device of claim 10 , wherein the replacement metal gate structure is on the one or more semiconductor nanosheet layer segments adjoining the source/drain.
12 . The backside power connection device of claim 9 , wherein a portion of the backside conductive contact is recessed below a surface of the backside interlevel dielectric layer.
13 . The backside power connection device of claim 12 , further comprising a dielectric fill layer on the backside conductive contact and the backside interlevel dielectric layer, wherein the backside via and the backside power rail are in the dielectric fill layer.
14 . A method of forming a semiconductor device, the method comprising:
forming a source/drain having a height, a length, and a width; and
forming a full wrap-around contact surrounding at least a partial length of the source/drain, wherein forming the full wrap-around contact includes:
forming a partial front-side wrap-around contact from a front side of a substrate; and
forming a partial back-side wrap-around contact from a back side of the substrate directly on a backside surface of the source/drain.
15 . The method of claim 14 , further comprising forming a metal-silicide layer on the source/drain, wherein the metal-silicide layer extends over insulating sidewalls adjacent the source/drain, and wherein at last a portion of the full wrap-around contact comprises a metal-silicide layer.
16 . The method of claim 15 , wherein a portion of the metal-silicide layer separates the partial front-side wrap-around contact from the source/drain.
17 . The method of claim 16 , wherein one or more semiconductor nanosheet layer segments adjoin the source/drain.
18 . The method of claim 17 , wherein a portion of the partial back-side wrap-around contact extends in a gap between a first interlayer dielectric layer and the source/drain.
19 . The method of claim 18 , wherein a replacement metal gate structure is on the one or more semiconductor nanosheet layer segments, and an inner spacer separates the replacement metal gate structure from the source/drain.
20 . The method of claim 19 , wherein the metal-silicide layer comprises nickel platinum silicide (NiPtSi).