Method of using semiconductor device and method of making
A method of biasing a substrate includes electrically connecting a silicide structure to a bias voltage supply. The method further includes conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures. The method further includes transferring the bias voltage from the silicide extension into a doped region of a substrate below the adjacent gate structures of the plurality of first gate structures.
1 . A method of biasing a substrate, the method comprises: electrically connecting a silicide structure to a bias voltage supply;
conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the main body is over a first doped region having a first dopant type, the silicide extension extends between adjacent gate structures of a plurality of first gate structures continuously extending in a first direction over the first doped region and a second doped region having a second dopant type opposite the first dopant type, and a location of the electrical connection of the bias voltage supply to the silicide structure is beyond a periphery of the plurality of first gate structures in the first direction; and
transferring the bias voltage from the silicide extension into the second doped region below the adjacent gate structures of the plurality of first gate structures.
2 . The method of claim 1 , wherein electrically connecting the silicide structure to the bias voltage supply comprises electrically connecting the silicide structure to the bias voltage supply using an interconnect structure.
3 . The method of claim 1 , wherein electrically connecting the silicide structure to the bias voltage supply comprises electrically connecting the silicide structure to the bias voltage supply using a through silicon via (TSV).
4 . The method of claim 1 , wherein transferring the bias voltage into the second doped region comprises transferring the bias voltage to the doped region from a portion of the silicide extension in direct contact with each of the plurality of first gate structures.
5 . A method of biasing a substrate, the method comprises:
electrically connecting a silicide structure to a bias voltage supply, wherein the silicide structure comprises a main body and a silicide extension;
conducting a bias voltage received by the silicide structure through the main body, wherein the main body is over a first doped region of a substrate, and the first doped region has a first dopant type;
conducting the bias voltage from the main body to the silicide extension, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures and over a second doped region of the substrate, and the second doped region has a second dopant type; and
transferring the bias voltage from the silicide extension into the second doped region below the adjacent gate structures of the plurality of first gate structures, wherein transferring the bias voltage from the silicide extensions comprises inhibiting transferring of the bias voltage into the first doped region.
6 . The method of claim 5 , wherein transferring the bias voltage from the silicide extension comprises transferring the bias voltage from a distal portion of the silicide extension, wherein the distal portion of the silicide extension is a farthest portion of the silicide extension from the main body.
7 . The method of claim 5 , wherein transferring the bias voltage from the silicide extension comprises transferring the bias voltage from a portion of the silicide extension having a greatest width.
8 . The method of claim 5 , wherein conductive the bias voltage through the main body comprises conducting the bias voltage along the main body entirely over the first doped region.
9 . The method of claim 5 , wherein conducting the bias voltage through the main body comprises conducting the bias voltage through the main body in direct contact with a first gate structure of the plurality of first gate structures.
10 . A method of making a semiconductor device, the method comprising:
doping a first region in a substrate with a first dopant type;
doping a second region in the substrate with a second dopant type opposite the first dopant type, wherein the second region is separated from the first region in a first direction;
forming a plurality of first gate structures on the substrate, wherein each of the plurality of first gate structures continuously extending in the first direction over the first doped region and the second doped region, wherein an interface of the first region and the second region exists in a space between adjacent first gate structures of the plurality of first gate structures, adjacent gates of the plurality of first gate structures are separated from each other in a second direction perpendicular to the first direction, and the second region extends beyond at least one of the plurality of first gate structures in the second direction;
forming a silicide structure on the substrate, wherein the silicide structure comprises a main body and a silicide extension, the silicide extension extends into the space between adjacent gate structures of the plurality of first gate structures and across the interface between the first region and the second region; and
forming an isolation structure between a portion of the first region and a portion of the second region.
11 . The method of claim 10 , wherein forming the plurality of first gate structures comprises forming each of the plurality of first gate structures having an I-shape.
12 . The method of claim 10 , further comprising forming a plurality of second gate structures, wherein each of the plurality of second gate structures has a T-shape.
13 . The method of claim 10 , wherein forming the silicide structure comprises forming a first portion of the silicide extension in direct contact with the adjacent gate structures of the plurality of first gate structures.
14 . The method of claim 13 , wherein forming the silicide structure comprises forming a second portion spaced from each of the adjacent gate structures of the plurality of first gate structures.
15 . The method of claim 10 , wherein forming the silicide structure comprises forming the silicide extension directly contacting an edge of each of the plurality of first gate structures, and the edge is a closest edge of each of the plurality of first gate structures to the main body.
16 . The method of claim 10 , wherein forming the isolation structure comprises forming the isolation structure between the portion of the first region and the portion of the second region beyond an outer edge of the plurality of first gate structures.
17 . The method of claim 10 , wherein forming the isolation structure comprises forming the isolation structure directly contacting the second region.
18 . The method of claim 16 , wherein forming the plurality of first gate structures comprises forming each of the plurality of first gate structures extending over the isolation region.
19 . The method of claim 10 , wherein forming the plurality of first gate structures comprises forming each of the plurality of first gate structures extending over the first doped region.
20 . The method of claim 10 , wherein forming the silicide structure comprises forming the silicide extension having a variable width.