Gate structure for semiconductor device
The present disclosure describes semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate and a gate structure over the substrate, where the gate structure can include two opposing spacers, a dielectric layer formed on side surfaces of the two opposing spacers, and a gate metal stack formed over the dielectric layer. A top surface of the gate metal stack can be below a top surface of the dielectric layer. An example benefit of the semiconductor structure is to improve structure integrity of tight-pitch transistors in integrated circuits.
1 . A method, comprising:
forming, on a substrate, a vertical structure comprising first and second nanostructured layers;
depositing a semiconductor layer on sidewalls of the vertical structure;
forming, on the substrate, an isolation structure adjacent to the vertical structure;
forming a sacrificial gate structure on the vertical structure and the isolation structure;
removing the semiconductor layer, the second nanostructured layer, and the sacrificial gate structure to form a recess;
forming a gate dielectric layer in the recess, comprising:
forming a first portion of the gate dielectric layer in a lower portion of the recess; and
forming a second portion of the gate dielectric layer in an upper portion of the recess; and
forming a gate electrode on the first portion of the gate dielectric layer, wherein a top surface of the gate electrode is below a top surface of the gate dielectric layer.
2 . The method of claim 1 , wherein the forming the gate electrode comprises:
forming a gate metal stack in the recess; and
selectively removing a portion of the gate metal stack formed on the second portion of the gate dielectric layer.
3 . The method of claim 1 , wherein forming the isolation structure comprises:
depositing a liner on the substrate;
depositing a first dielectric layer on the liner; and
depositing a second dielectric layer on the liner and the first dielectric layer.
4 . The method of claim 1 , further comprising depositing a semiconductor layer on sidewalls of the vertical structure prior to forming the isolation structure.
5 . The method of claim 1 , wherein forming the gate electrode comprises depositing a metal layer between the first nanostructured layer and the isolation structure.
6 . A method, comprising:
forming, on a semiconductor substrate, vertical structures having sacrificial layers and channel regions comprising one or more doped semiconductor materials;
depositing semiconductor layers on sidewalls of the vertical structures;
forming isolation structures between the vertical structures;
forming a sacrificial gate structure on top surfaces of the vertical structures and the isolation structures and on sidewalls of the semiconductor layers;
forming opposing gate spacers adjacent to the sacrificial gate structure;
removing the semiconductor layer, the sacrificial layers, and the sacrificial gate structure;
forming a gate dielectric layer on the isolation structures and the channel regions; and
forming a gate metal stack on the gate dielectric layer, wherein the gate dielectric layer and the opposing gate spacers extend above a top surface of the gate metal stack.
7 . The method of claim 6 , further comprising forming a padding layer on the gate metal stack and the isolation structure.
8 . The method of claim 6 , wherein forming the gate metal stack comprises forming the gate metal stack between the channel regions and the isolation structure.
9 . The method of claim 6 , wherein forming the gate metal stack comprises depositing the gate metal stack on sidewalls of the isolation structure.
10 . The method of claim 6 , wherein forming the gate dielectric layer comprises forming a top surface of the gate dielectric layer coplanar with top surfaces of the opposing gate spacers.
11 . The method of claim 6 , further comprising removing the semiconductor layers prior to forming the gate dielectric layer.
12 . The method of claim 6 , wherein depositing the semiconductor layers comprises depositing silicon germanium layers.
13 . A method, comprising:
forming, on a substrate, a first vertical structure, the first vertical structure comprising a channel region and a sacrificial layer;
depositing semiconductor layers on sidewalls of the first vertical structure;
forming, on the substrate, a second vertical structure over the substrate and on sidewalls of the semiconductor layer, the second vertical structure comprising a dielectric stack;
forming a sacrificial gate structure over the channel region of the first vertical structure;
forming two opposing spacers along sidewalls of the sacrificial gate structure;
forming a first dielectric layer over side surfaces of the two opposing spacers, the first dielectric layer comprising two opposing side surfaces and top surfaces substantially coplanar with top surfaces of the two opposing spacers;
removing the sacrificial layer, the semiconductor layers, and the sacrificial gate structure; and
forming a gate metal stack between the two opposing side surfaces of the first dielectric layer, wherein a top surface of the gate metal stack is below the top surfaces of the first dielectric layer.
14 . The method of claim 13 , wherein forming the gate metal stack comprises forming the top surface of the gate metal stack below a top surface of the second vertical structure.
15 . The method of claim 13 , wherein forming the first dielectric layer comprises depositing the first dielectric layer on the channel region and the dielectric stack.
16 . The method of claim 13 , wherein forming the dielectric stack of the second vertical structure comprises forming a second dielectric layer and a third dielectric layer disposed over the second dielectric layer, wherein the second dielectric layer comprises a low-k dielectric material and the third dielectric layer comprises hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO x ), hafnium silicon oxide (HfSiO x ), or a high-k dielectric material.
17 . The method of claim 13 , wherein forming the channel region of the first vertical structure comprises forming a layer of silicon or silicon-germanium.
18 . The method of claim 13 , wherein forming the gate metal stack comprises:
depositing a metal layer on the first dielectric layer; and
etching the metal layer to expose a top portion of the first dielectric layer.
19 . The method of claim 13 , wherein forming the first vertical structure comprises forming the first vertical structure with a top surface below a top surface of the second vertical structure.
20 . The method of claim 13 , further comprising depositing an insulating layer on a top surface of the gate metal stack and on a top surface and sidewalls of the second vertical structure.