Integrated circuit and method of manufacturing the same
An integrated circuit including a plurality of stacked metal layers and a method of manufacturing the integrated circuit are provided. The method includes: providing a plurality of standard cells, each of which includes cell patterns respectively formed on the plurality of metal layers; and forming, on a particular metal layer among the plurality of metal layers which includes patterns extending in a first direction that are respectively formed on a plurality of tracks that are spaced apart from each other in a second direction, an additional pattern between adjacent patterns formed on a particular track of the plurality of tracks based on an interval between the adjacent patterns exceeding a reference value.
1 . A method of manufacturing an integrated circuit comprising a plurality of metal layers, which are stacked, the method comprising:
providing a plurality of standard cells, each of which comprises a plurality of patterns respectively formed on the plurality of metal layers; and
forming, on a metal layer among the plurality of metal layers which comprises patterns extending in a first direction that are respectively formed on a plurality of tracks that are spaced apart in a second direction, an extension pattern between adjacent patterns formed on a first track among the plurality of tracks based on an interval between the adjacent patterns exceeding a reference value,
wherein the adjacent patterns and the extension pattern comprise a conductive material, and
wherein the extension pattern extends from one of the adjacent patterns.
2 . The method of claim 1 , further comprising forming a dummy pattern on a second track among the plurality of tracks,
wherein the dummy pattern extends over a first standard cell, a second standard cell, and a cell boundary between the first standard cell and the second standard cell.
3 . The method of claim 2 , wherein the dummy pattern comprises a conductive material.
4 . The method of claim 1 , wherein the forming the extension pattern comprises forming the extension pattern extending from a pattern of a first standard cell among the plurality of standard cells.
5 . The method of claim 4 , wherein the forming the extension pattern comprises forming the extension pattern over the first standard cell and a second standard cell adjacent to the first standard cell.
6 . The method of claim 4 , further comprising forming a via which connects the extension pattern to a pattern of another layer of the plurality of metal layers.
7 . The method of claim 1 , wherein the adjacent patterns formed on an identical track among the plurality of tracks are spaced apart by at least one designated value.
8 . The method of claim 1 , wherein the plurality of standard cells are electrically connected to a plurality of power rails extending in the first direction.
9 . The method of claim 1 , wherein the plurality of standard cells are electrically connected to a plurality of power rails extending in the second direction.
10 . An integrated circuit comprising a plurality of metal layers, which are stacked, the integrated circuit comprising:
a first logic cell and a second logic cell, at least one of which comprising a plurality of patterns respectively formed on the plurality of metal layers, wherein a first metal layer among the plurality of metal layers comprises patterns extending in a first direction and a plurality of first tracks spaced apart in a second direction; and
a dummy pattern formed on a first track among the plurality of first tracks over the first logic cell, the second logic cell and a cell boundary between the first logic cell and the second logic cell in the first metal layer, wherein the dummy pattern is separated from other patterns on the first metal layer,
wherein the dummy pattern comprises a conductive material.
11 . The integrated circuit of claim 10 , wherein the plurality of metal layers are provided on a substrate, and
wherein among the plurality of metal layers, the first metal layer is closest to the substrate.
12 . The integrated circuit of claim 10 , wherein the first logic cell and the second logic cell have an identical cell height in the first direction.
13 . The integrated circuit of claim 10 , wherein the first logic cell and the second logic cell have different cell heights in the first direction,
wherein the plurality of metal layers are provided on a substrate, wherein, a second metal layer, among the plurality of metal layers, provided between the substrate and the first metal layer, comprises patterns extending in the second direction and a plurality of second tracks spaced apart in the first direction, and
wherein, among the plurality of second tracks, a number of second tracks passing through a cell boundary of the first logic cell is different from a number of second tracks passing through a cell boundary of the second logic cell.
14 . The integrated circuit of claim 10 , wherein two patterns disposed adjacent to each other on the same first track among the plurality of first tracks are spaced apart by at least one designated value.
15 . The integrated circuit of claim 10 , further comprising an extension pattern formed on the first metal layer, and extending from a pattern of the first logic cell.
16 . An integrated circuit comprising a plurality of metal layers, which are stacked, the integrated circuit comprising:
a first standard cell and a second standard cell, at least one of which comprises a plurality of patterns respectively formed on the plurality of metal layers, wherein a metal layer among the plurality of metal layers comprises patterns extending in a first direction and a plurality of first tracks spaced apart in a second direction; and
an extension pattern formed on a first track among the plurality of first tracks over the first standard cell and the second standard cell in the metal layer, wherein the extension pattern is formed between two patterns on the first track and extends from a pattern among the two patterns,
wherein the extension pattern extends from one of the two patterns,
wherein the two patterns are adjacent each other and spaced apart by at least one designated value, and
wherein the two patterns and the extension pattern comprise a conductive material.
17 . The integrated circuit of claim 16 , further comprising a dummy pattern on a second track among the plurality of first tracks,
wherein the dummy pattern is electrically separated from other patterns in other first tracks among the plurality of first tracks, and
wherein the dummy pattern extends over a cell boundary between the first standard cell and the second standard cell.
18 . The integrated circuit of claim 17 , wherein the dummy pattern comprises a conductive material.
19 . The integrated circuit of claim 16 , wherein the first standard cell and the second standard cell have different cell heights from each other in the first direction.
20 . The integrated circuit of claim 16 , further comprising a dummy pattern extending over the first standard cell, the second standard cell, and a cell boundary between the first standard cell and the second standard cell,
wherein the dummy pattern is electrically separated from other patterns on the metal layer.