Method and structure for reduced substrate loss for GaN devices
An integrated circuit includes a GaN layer located over a semiconductor substrate. The GaN layer includes an active device region of the GaN layer having a first conductivity and a passive device region of the GaN layer having a smaller second conductivity. A transistor may be located over the GaN layer in the active device region, and a passive device may be located over the GaN layer in the passive device region.
1 . A method of forming an integrated circuit, comprising:
forming a GaN layer over a semiconductor substrate;
decreasing conductivity of the GaN layer in a passive device region by amorphizing the GaN layer in the passive device region; and
forming a GaN transistor in an active device region of the GaN layer, the decreasing the conductivity of the GaN layer including:
forming a plurality of first voids in a first dielectric layer that overlies the GaN layer, the first voids extending through the first dielectric layer and into the GaN layer;
filling a top portion of the first voids with a first dielectric filler, while leaving an unfilled lower portion of the first voids;
forming a plurality of second voids in a second dielectric layer that overlies the first dielectric layer; and
filling the second voids with a second dielectric filler.
2 . The method of claim 1 , wherein the first dielectric layer comprises SiN.
3 . The method of claim 2 , further comprising forming a passive device between the plurality of first voids and the plurality of second voids.
4 . The method of claim 3 , wherein the passive device includes an inductive coil.
5 . The method of claim 1 , wherein the first dielectric filler includes hydrogen-silsesquioxane or methyl-silsesquioxane.
6 . The method of claim 1 , wherein the first dielectric filler includes a high-density plasma oxide.
7 . The method of claim 1 , wherein the second dielectric layer includes silicon oxide.
8 . The method of claim 1 , wherein the second dielectric parallel trenches.
9 . The method of claim 1 , wherein the first voids include round holes.
10 . A method of forming an integrated circuit, comprising:
forming a GaN layer over a semiconductor substrate;
amorphizing the GaN layer in a passive device region;
forming a plurality of first voids in a first dielectric layer that overlies the passive device region, the first voids extending through the first dielectric layer and into the GaN layer;
filling a top portion of the first voids with a first dielectric filler, while leaving an unfilled lower portion of the first voids;
forming a plurality of second voids in a second dielectric layer that overlies the first dielectric layer;
filling the second voids with a second dielectric filler; and
forming a GaN transistor in an active device region of the GaN layer.
11 . The method of claim 10 , wherein the first dielectric layer comprises SiN.
12 . The method of claim 11 , further comprising forming a passive device over the plurality of first voids.
13 . The method of claim 12 , wherein the passive device includes an inductive coil.
14 . The method of claim 10 , wherein the first dielectric filler includes hydrogen-silsesquioxane or methyl-silsesquioxane.
15 . The method of claim 10 , wherein the first dielectric filler includes a high-density plasma oxide.
16 . The method of claim 10 , wherein the second dielectric layer includes silicon oxide.
17 . The method of claim 10 , wherein the first voids include parallel trenches.
18 . The method of claim 10 , wherein the first voids include round holes.