IP Library › Granted Patent US 12713688
Granted Patent B2
US 12713688 · App. 18/321,483 · Granted Aug 18, 2026

CFET with different channel materials for NFET and PFET and methods for forming the same

Inventor: Marcus Johannes Henricus van Dal (Linden, BE)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H10D84/038H10D84/0167H10D84/017H10D84/0193H10D84/853H10D84/856H10D88/00
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Quick Facts
Patent No.
US 12713688
App. No.
18/321,483
Granted
Aug 18, 2026
Kind
B2
Abstract

A method includes forming a Complimentary Field-Effect Transistor (CFET) including forming an n-type transistor and a p-type transistor overlapping the n-type transistor. The formation of the n-type transistor includes forming a first channel region comprising a first semiconductor material, and forming an n-type source/drain region on a side of, and connecting to, the first channel region. The formation of the p-type transistor includes forming a second channel region comprising a second semiconductor material different from the first semiconductor material, and forming a p-type source/drain region on a side of, and connecting to, the second channel region.

Claims (51)

1 . A method comprising:

forming a Complimentary Field-Effect Transistor (CFET) comprising:

forming an n-type transistor comprising:

forming a first channel region comprising a first semiconductor material, wherein the forming the first channel region comprises:

depositing a silicon layer and a first silicon germanium layer contacting the silicon layer;

removing the first silicon germanium layer, with the silicon layer being left as the first channel region; and

forming an n-type source/drain region on a side of, and connecting to, the first channel region; and

forming a p-type transistor overlapping the n-type transistor, the forming the p-type transistor comprising:

forming a second channel region comprising a second semiconductor material different from the first semiconductor material, wherein the forming the second channel region comprises:

depositing a germanium layer and a second silicon germanium layer contacting the germanium layer; and

removing the second silicon germanium layer, with the germanium layer being left as the second channel region; and

forming a p-type source/drain region on a side of, and connecting to, the second channel region.

2 . The method of claim 1 , wherein the forming the second channel region is performed after both of the first channel region and the n-type source/drain region are formed.

3 . The method of claim 1 , wherein the forming the second channel region is performed before both of the first channel region and the n-type source/drain region are formed.

4 . The method of claim 1 further comprising:

forming a first interconnect structure connecting to the n-type transistor; and

forming a second interconnect structure connecting to the p-type transistor, wherein the first interconnect structure and the second interconnect structure are on opposite sides of the CFET.

5 . The method of claim 1 , wherein the n-type transistor is formed on a dielectric layer, and wherein the p-type transistor is formed on an opposite side of the dielectric layer than the n-type transistor.

6 . The method of claim 5 , wherein the n-type source/drain region and the p-type source/drain region are in contact with the dielectric layer.

7 . The method of claim 6 further comprising a source/drain via in the dielectric layer, wherein the source/drain via electrically connects the n-type source/drain region to the p-type source/drain region.

8 . The method of claim 5 , wherein the n-type transistor comprises a first gate electrode contacting the dielectric layer, and the p-type transistor comprises a second gate electrode contacting the dielectric layer.

9 . The method of claim 8 further comprising forming a gate via in the dielectric layer, wherein the gate via electrically connects the first gate electrode to the second gate electrode.

10 . A device comprising:

a dielectric layer;

an n-type transistor under the dielectric layer, the n-type transistor comprising:

a first channel region comprising a first semiconductor material; and

an n-type source/drain region on a side of and connecting to the first channel region; and

a p-type transistor over the dielectric layer, the p-type transistor comprising:

a second channel region comprising a second semiconductor material different from the first semiconductor material; and

a p-type source/drain region on a side of and connecting to the second channel region, wherein at least one of the n-type source/drain region and the p-type source/drain region are in contact with the dielectric layer.

11 . The device of claim 10 , wherein the second channel region has a higher germanium atomic percentage than the first channel region.

12 . The device of claim 11 , wherein the first channel region comprises silicon and is free from germanium, and the second channel region comprises germanium and is free from silicon.

13 . The device of claim 10 , wherein both of the n-type source/drain region and the p-type source/drain region are in contact with the dielectric layer.

14 . The device of claim 13 further comprising a source/drain via in the dielectric layer, wherein the source/drain via electrically connects the n-type source/drain region to the p-type source/drain region.

15 . The device of claim 10 , wherein the n-type transistor comprises a first gate electrode contacting the dielectric layer, and the p-type transistor comprises a second gate electrode contacting the dielectric layer.

16 . The device of claim 15 further comprising a gate via in the dielectric layer, wherein the gate via electrically connects the first gate electrode to the second gate electrode.

17 . A device comprising:

a first transistor comprising:

a silicon channel;

a first gate stack encircling the silicon channel; and

a first source/drain region on a side of and joined to the silicon channel;

a dielectric layer over and physically contacting the first gate stack; and

a second transistor overlapping both of the dielectric layer and the first transistor, the second transistor comprising:

a germanium channel;

a second gate stack encircling the germanium channel, wherein the second gate stack further contacts the dielectric layer; and

a second source/drain region on a side of and joined to the germanium channel, wherein one of the first source/drain region and the second source/drain region forms a first interface with the dielectric layer.

18 . The device of claim 17 further comprising a gate via comprising a top surface contacting the first gate stack, and a bottom surface contacting the second gate stack.

19 . The device of claim 17 , wherein the first source/drain region forms the first interface with the dielectric layer, and the second source/drain region forms a second interface with the dielectric layer, and wherein the first interface is parallel to the second interface.

20 . The device of claim 17 further comprising a source/drain via electrically coupling the first source/drain region to the second source/drain region, wherein the source/drain via comprises:

a first surface coplanar with a second surface of the dielectric layer; and

a third surface coplanar with a fourth surface of the dielectric layer, wherein the first surface and the third surface are opposing surfaces of the source/drain via.