Gate cut grid across integrated circuit
Techniques are provided herein to form an integrated circuit having a grid of gate cut structures such that a gate cut structure exists between pairs of semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. Each of the gate cut structures may be formed at the same time in a grid-like pattern across the integrated circuit (or a portion thereof). Sidewall spacer structures on the sidewalls of the gate structure wrap around ends of each gate structure to form a given gate cut structure.
1 . An integrated circuit comprising:
a first semiconductor device having a first semiconductor body extending in a first direction between a first source region and a first drain region;
a second semiconductor device having a second semiconductor body extending in the first direction parallel to the first semiconductor body between a second source region and a second drain region;
a first gate structure extending across the first semiconductor body in a second direction different from the first direction;
a second gate structure extending across the second semiconductor body in the second direction colinearly with the first gate structure;
a first spacer structure along sidewalls of the first gate structure; and
a second spacer structure along sidewalls of the second gate structure;
wherein the first and second spacer structures wrap around ends of the first and second gate structures, respectively, and contact one another to form a gate cut structure between the first gate structure and the second gate structure, the gate cut structure extending in a third direction along an entire height of the first semiconductor body and an entire height of the second semiconductor body.
2 . The integrated circuit of claim 1 , wherein the first semiconductor body and the second semiconductor body each comprises a plurality of semiconductor nanoribbons.
3 . The integrated circuit of claim 1 , wherein the first gate structure comprises a first gate dielectric layer around the first semiconductor body and the second gate structure comprises a second gate dielectric layer around the second semiconductor body.
4 . The integrated circuit of claim 3 , wherein the first gate dielectric layer is present on a first sidewall of the gate cut structure and the second gate dielectric layer is present on a second sidewall of the gate cut structure.
5 . The integrated circuit of claim 1 , wherein the gate cut structure is a first gate cut structure, and the first and second gate structures provide a first gate structure pair, the integrated circuit comprising:
a second gate structure pair including a third gate structure and a fourth gate structure, the third and fourth gate structures collinear with each other as well as with the first and second gate structures;
a second gate cut structure between the first gate structure pair and the second gate structure pair; and
a third gate cut structure between the third gate structure and the fourth gate structure.
6 . The integrated circuit of claim 1 , further comprising a conductive layer over a top surface of the gate cut structure, the conductive layer in direct contact with each of the first gate structure and the second gate structure.
7 . The integrated circuit of claim 1 , wherein the first and second spacer structures pinch inwards to form the gate cut structure.
8 . The integrated circuit of claim 1 , wherein the gate cut structure has a dimpled or pinched-in profile.
9 . A printed circuit board comprising the integrated circuit of claim 1 .
10 . An electronic device, comprising:
a chip package comprising one or more dies, at least one of the one or more dies comprising
a first semiconductor device having a first semiconductor body extending in a first direction between a first source region and a first drain region;
a second semiconductor device having a second semiconductor body extending in the first direction parallel to the first semiconductor body between a second source region and a second drain region;
a first gate structure extending across the first semiconductor body in a second direction different from the first direction;
a second gate structure extending across the second semiconductor body in the second direction colinearly with the first gate structure;
a first spacer structure along sidewalls of the first gate structure; and
a second spacer structure along sidewalls of the second gate structure;
wherein the first and second spacer structures wrap around ends of the first and second gate structures, respectively, and contact one another to form a gate cut structure between the first gate structure and the second gate structure, the gate cut structure extending in a third direction along an entire height of the first semiconductor body and an entire height of the second semiconductor body.
11 . The electronic device of claim 10 , wherein the first semiconductor body and the second semiconductor body each comprises a plurality of semiconductor nanoribbons.
12 . The electronic device of claim 10 , wherein the first gate structure comprises a first gate dielectric layer around the first semiconductor body and the second gate structure comprises a second gate dielectric layer around the second semiconductor body.
13 . The electronic device of claim 12 , wherein the first gate dielectric layer is present on a first sidewall of the gate cut structure and the second gate dielectric layer is present on a second sidewall of the gate cut structure.
14 . The electronic device of claim 10 , further comprising a conductive layer over a top surface of the gate cut structure, such that the conductive layer directly contacts each of the first gate structure and the second gate structure.
15 . The electronic device of claim 10 , wherein the first and second spacer structures pinch inwards to form the gate cut structure.
16 . An integrated circuit comprising:
a plurality of semiconductor devices each having one or more semiconductor bodies extending in a first direction between a corresponding source region and a corresponding drain region;
a plurality of gate structures, each gate structure extending lengthwise in a second direction different from the first direction and around the one or more semiconductor bodies of a corresponding semiconductor device of the plurality of semiconductor devices; and
a plurality of dielectric barriers, wherein each dielectric barrier is arranged between a different pair of gate structures that are collinear along the second direction, such that each dielectric barrier extends in the first direction and divides the pair of gate structures, wherein each dielectric barrier comprises a first spacer structure wrapped around an end of a first gate structure of the pair of gate structures and a second spacer structure wrapped around an end of a second gate structure of the pair of gate structures, the first spacer structure contacting the second spacer structure and the second gate structure being colinearly aligned with the first gate structure, and wherein each dielectric barrier extends in a third direction along an entire height of the one or more semiconductor bodies of corresponding adjacent semiconductor devices.
17 . The integrated circuit of claim 16 , wherein the semiconductor bodies each comprise a plurality of semiconductor nanoribbons.
18 . The integrated circuit of claim 16 , further comprising a conductive layer over a top surface of a given one of the dielectric barriers, such that the conductive layer directly contacts a first gate structure on a first side of the given dielectric barrier and directly contacts a second gate structure on an opposite second side of the given dielectric barrier.
19 . The integrated circuit of claim 16 , wherein the first spacer structure also extends lengthwise in the second direction along a sidewall of the first gate structure, and the second spacer structure also extends lengthwise in the second direction along a sidewall of the second gate structure.
20 . The integrated circuit of claim 16 , wherein the first and second spacer structures pinch inwards to form a given dielectric barrier.