IP Library Granted Patent US 12713694
Granted Patent B2
US 12713694 · App. 18/314,484 · Granted Aug 18, 2026

Semiconductor device having merged epitaxial pattern and method for fabricating the same

Inventors: Kyung ho Kim (Suwon-si, KR); Myung Il Kang (Suwon-si, KR); Sung Uk Jang (Suwon-si, KR); Kyung Hee Cho (Suwon-si, KR); Do Young Choi (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D84/856H10D30/014H10D30/43H10D30/6729H10D30/6735H10D62/121H10D64/017H10D84/0167H10D84/0188H10D84/038H10D88/01
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Quick Facts
Patent No.
US 12713694
App. No.
18/314,484
Granted
Aug 18, 2026
Kind
B2
Abstract

A semiconductor device includes a substrate, a first active pattern disposed on the substrate, a second active pattern stacked on the first active pattern, a first gate structure extending to intersect the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure and extending to intersect the first active pattern and the second active pattern, a first epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the first active pattern, a second epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the second active pattern, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern.

Claims (59)

1 . A semiconductor device comprising:

a substrate;

a first active pattern disposed on the substrate and extending in a first direction;

a second active pattern stacked on the first active pattern and extending in the first direction;

a first gate structure extending in a second direction to intersect the first active pattern and the second active pattern, the second direction intersecting the first direction;

a second gate structure spaced apart from the first gate structure in the first direction and extending in the second direction to intersect the first active pattern and the second active pattern;

a first epitaxial pattern interposed between the first gate structure and the second gate structure, the first epitaxial pattern connected to the first active pattern;

a second epitaxial pattern interposed between the first gate structure and the second gate structure, the second epitaxial pattern connected to the second active pattern;

an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern; and

a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern,

wherein a top surface of the first epitaxial pattern has a contact recess recessed toward the substrate.

2 . The semiconductor device of claim 1 , wherein the semiconductor film includes a polysilicon film.

3 . The semiconductor device of claim 1 , wherein a spacing between the first gate structure and the second gate structure is equal to or larger than about 15 nm.

4 . The semiconductor device of claim 1 , wherein the second epitaxial pattern includes a polycrystalline film.

5 . The semiconductor device of claim 1 , wherein a top surface of the second epitaxial pattern includes:

a flat surface parallel to a top surface of the substrate;

a first inclined surface disposed between the first gate structure and the flat surface; and

a second inclined surface disposed between the second gate structure and the flat surface,

wherein an angle defined between each of the first inclined surface and the second inclined surface and the flat surface is an obtuse angle.

6 . The semiconductor device of claim 5 , wherein a bottom surface of the second epitaxial pattern is parallel to the top surface of the substrate.

7 . The semiconductor device of claim 1 , wherein the second epitaxial pattern includes an epitaxial layer grown using the second active pattern and the semiconductor film as seed layers.

8 . The semiconductor device of claim 1 , further comprising an isolation pattern interposed between the first active pattern and the second active pattern,

wherein the insulating pattern is disposed on a side surface of the isolation pattern.

9 . The semiconductor device of claim 8 , further comprising a liner film interposed between the isolation pattern and the insulating pattern,

wherein the semiconductor film extends along the top surface of the insulating pattern and a top surface of the liner film.

10 . The semiconductor device of claim 1 , wherein the first active pattern includes a plurality of lower sheet patterns sequentially stacked on the substrate and spaced apart from each other, each of the plurality of lower sheet patterns extending in the first direction, and

wherein the second active pattern includes a plurality of upper sheet patterns sequentially stacked on the first active pattern and spaced apart from each other, each of the plurality of upper sheet patterns extending in the first direction.

11 . A semiconductor device comprising:

a substrate;

a first active pattern disposed on the substrate and extending in a first direction;

a second active pattern stacked on the first active pattern and extending in the first direction;

a gate structure disposed on the substrate and extending in a second direction intersecting the first direction, each of the first active pattern and the second active pattern passing through the gate structure;

a first epitaxial pattern disposed on a side surface of the gate structure, and connected to the first active pattern;

a second epitaxial pattern disposed on the side surface of the gate structure and connected to the second active pattern;

an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern; and

a semiconductor film interposed between the insulating pattern and the second epitaxial pattern,

wherein the second epitaxial pattern includes an epitaxial layer grown using the second active pattern and the semiconductor film as seed layers, and

wherein a top surface of the first epitaxial pattern has a contact recess recessed toward the substrate.

12 . The semiconductor device of claim 11 , wherein the semiconductor film includes a polycrystalline semiconductor material.

13 . The semiconductor device of claim 12 , wherein a lower portion of the second epitaxial pattern adjacent to the semiconductor film is polycrystalline.

14 . The semiconductor device of claim 11 , wherein the semiconductor film is formed using a directional deposition process.

15 . The semiconductor device of claim 11 , wherein the first epitaxial pattern includes an epitaxial layer grown using the substrate and the first active pattern as seed layers.

16 . A semiconductor device comprising:

a substrate;

a plurality of lower sheet patterns sequentially stacked on the substrate, and spaced apart from each other, wherein each of the plurality of lower sheet patterns extends in a first direction;

a plurality of upper sheet patterns sequentially stacked on the plurality of lower sheet patterns, and spaced apart from each other, wherein each of the plurality of upper sheet patterns extends in the first direction;

an isolation pattern interposed between the plurality of lower sheet patterns and the plurality of upper sheet patterns;

a gate structure disposed on the substrate and extending in a second direction intersecting the first direction, wherein each of the plurality of lower sheet patterns and each of the plurality of upper sheet patterns pass through the gate structure;

a first epitaxial pattern disposed on a side surface of the gate structure, and connected to the plurality of lower sheet patterns, wherein the first epitaxial pattern has a first conductivity type;

a second epitaxial pattern disposed on the side surface of the gate structure, and connected to the plurality of upper sheet patterns, wherein the second epitaxial pattern has a second conductivity type different from the first conductivity type;

an insulating pattern disposed on a side surface of the isolation pattern and interposed between the first epitaxial pattern and the second epitaxial pattern; and

a polysilicon film disposed between the insulating pattern and the second epitaxial pattern and extending along a top surface of the insulating pattern,

wherein a top surface of the first epitaxial pattern has a contact recess recessed toward the substrate.

17 . The semiconductor device of claim 16 , further comprising a liner film interposed between the isolation pattern and the insulating pattern,

wherein the polysilicon film extends along the top surface of the insulating pattern and a top surface of the liner film.

18 . The semiconductor device of claim 17 , wherein the insulating pattern includes silicon oxide, and

wherein the liner film includes silicon nitride.

19 . The semiconductor device of claim 16 , further comprising a lower source/drain contact disposed between the first epitaxial pattern and the insulating pattern and electrically connected to the first epitaxial pattern.

20 . The semiconductor device of claim 16 , further comprising an upper source/drain contact disposed on the second epitaxial pattern and electrically connected to the second epitaxial pattern.